At the Global Foundries Technology Conference, AMD’s CTO Mark Papermaster announced that the company will be transitioning “graphics and client products” from the Global Foundries 14nm LP FinFET process it uses today to the new 12LP process in 2018.
This article says that AMD is shrinking Ryzen and Vega for 2018. I've read in the past that they plan to integrate those two chips together to make a successor to their hybrid CPU line.
If that was the case, can Vega use DDR4 system memory when it was designed for HBM2? As an engineer, do you just swap out the memory controllers and you're good to go?
If that was the case, can Vega use DDR4 system memory when it was designed for HBM2? As an engineer, do you just swap out the memory controllers and you're good to go?
Vega is the codename for the particular piece of silicon powering Vega 56/64. The underlying mico-architecture of Vega is GCN 5th Gen, and I don't see why they wouldn't be able to use it with alternate memory types.
For example, GCN 3rd Gen was used in Tonga (R9 285, 380(X) w/ GDDR5), Fiji (Fury (X)/ Nano w/ HBM), and Bristol Ridge APUs (DDR4).
If that was the case, can Vega use DDR4 system memory when it was designed for HBM2? As an engineer, do you just swap out the memory controllers and you're good to go?
Vega is the codename for the particular GPU powering the Vega 56/64 graphics cards. The underlying GPU architecture of Vega is GCN 5th Gen, and I don't see why they wouldn't be able to use it with alternate memory types. For example, GCN 3rd Gen was used in Tonga (R9285, 380(X) w/ GDDR5), Fiji (Fury (X)/ Nano w/ HBM), and Bristol Ridge APUs (DDR4).
Yes but wasn't the new architecture designed for HBM? The onboard graphics CPU from AMD uses DDR4 system memory which is slower than HBM...I'm also curious if there will be any memory on die dedicated to the graphics chip...if not, will performance be much lower using DDR4?
What amazes me is that when I REALLY got into PC's the PIII just came out. To think that was 250nm and now here we are talking about 7nm. all this in less than 20 years.
What amazes me is that when I REALLY got into PC's the PIII just came out. To think that was 250nm and now here we are talking about 7nm. all this in less than 20 years.
Yeah technology moves damn fast...makes me wonder why reprogrammable CPUs haven't been explored... imagine being able to recode older CPUs with newer instructions...that could extend the life of a CPU for many years...I do believe Intel explored this possibility but it was abandoned pretty quickly.
This article says that AMD is shrinking Ryzen and Vega for 2018. I've read in the past that they plan to integrate those two chips together to make a successor to their hybrid CPU line.
If that was the case, can Vega use DDR4 system memory when it was designed for HBM2? As an engineer, do you just swap out the memory controllers and you're good to go?
Vega's high bandwidth cache controller can already directly access system ram, and potentially storage, or even other pci-e devices. There's also already a Vega professional card coming that has 2TB of onboard NAND flash connected via AMD's infinity fabric.
Yeah technology moves damn fast...makes me wonder why reprogrammable CPUs haven't been explored... imagine being able to recode older CPUs with newer instructions...that could extend the life of a CPU for many years...I do believe Intel explored this possibility but it was abandoned pretty quickly.
That's basically what an FPGA is (or rather, something that an FPGA could do), and they've been around for decades. Intel somewhat recently bought Altera (major FPGA producer), and I believe they are planning on (or already have) put FPGAs into some of they're Xeon processors.
But that doesn't magically extend the life of the CPU. You're still stuck on the same process (meaning same or similar clock speeds) with the same number of transistors. You could in theory reprogram parts of the FPGA to provide hardware acceleration for very specific tasks (which I believe is the idea behind the FPGA module on Xeons), but you can't just reconfigure the whole thing and get a faster CPU out of nowhere. Also, I'm pretty sure the FPGA required to implement a contemporary CPU would be much more expensive than the regular CPU would be.
A "vega + Zen" APU would not contain any large amount of memory. You can't simply add HBM memory then expect things to work properly with modern Operating Systems like Windows.
It's also a BUDGET solution anyway since the amount of GPU die space is limited so it makes no sense to increase the cost.
Now for MOBILE devices that have no memory expansion it MAY make sense to use an APU or SoC (system on chip) that has HBM memory acting as a shared CPU/GPU memory though I suspect there's no current market for that approach
Also Vega's HBM controller is NOT the same idea as having fast, close memory to the APU. That's a lot of added latency to talk to something much slower, so the SOFTWARE for the program must be designed to work with it to swap data to and from slower memory to shared system memory in a logical way.
Vega is the codename for the particular piece of silicon powering Vega 56/64. The underlying mico-architecture of Vega is GCN 5th Gen, and I don't see why they wouldn't be able to use it with alternate memory types.
For example, GCN 3rd Gen was used in Tonga (R9 285, 380(X) w/ GDDR5), Fiji (Fury (X)/ Nano w/ HBM), and Bristol Ridge APUs (DDR4).
Yes but wasn't the new architecture designed for HBM? The onboard graphics CPU from AMD uses DDR4 system memory which is slower than HBM...I'm also curious if there will be any memory on die dedicated to the graphics chip...if not, will performance be much lower using DDR4?
This is what I'm trying to get at. Vega56 and Vega64, while fundamentally being GCN architecture, were both designed with HBM2 in mind. I remember hearing in the case of the Fury cards that using HBM inherently changed the layout of the silicone. The whole chip was smaller and more compact than the way a GDDR5 chip is designed. Fury had no variants with GDDR5.
A good analogy would be with Athlon 64 and it's integrated memory controller in 2003. The memory controller ONLY supported DDR memory. AMD finally changed this with Phenom (maybe?) when they started integrating DDR2 controllers.
Coming back to my original post, Vega chips were inherently build with HBM2 in mind. They have a crazy 2048-bit bus to accommodate it. If AMD was planning to integrated Vega into Ryzen to make an APU, don't they have to tear out the HBM2 parts of the chip to make it work with DDR4 system ram?
Now that I've slept on it, I think what will happen is they'll have to make a new chip based loosely on Vega's architectural improvements but with full support for system memory. They've had to do that up until now with GDDR5 graphics cards.
Vega is the codename for the particular piece of silicon powering Vega 56/64. The underlying mico-architecture of Vega is GCN 5th Gen, and I don't see why they wouldn't be able to use it with alternate memory types.
For example, GCN 3rd Gen was used in Tonga (R9 285, 380(X) w/ GDDR5), Fiji (Fury (X)/ Nano w/ HBM), and Bristol Ridge APUs (DDR4).
Yes but wasn't the new architecture designed for HBM? The onboard graphics CPU from AMD uses DDR4 system memory which is slower than HBM...I'm also curious if there will be any memory on die dedicated to the graphics chip...if not, will performance be much lower using DDR4?
This is what I'm trying to get at. Vega56 and Vega64, while fundamentally being GCN architecture, were both designed with HBM2 in mind. I remember hearing in the case of the Fury cards that using HBM inherently changed the layout of the silicone. The whole chip was smaller and more compact than the way a GDDR5 chip is designed. Fury had no variants with GDDR5.
Sure, the specific chip used for Vega56/64 was designed with HBM in mind. But it's not like they're going to just throw that same Vega die into a package with a CPU to make an APU. First off it's way to big and power hungry (and powerful) for a APU, and secondly I don't think AMD APUs have historically been multi chip modules. They were always going to have to redesign the silicon regardless.
RE: Fury. I don't think it changed the layout of the GPU so much as it changed the layout of the package and PCB, due to having the memory modules on-package in contrast to GDDR5 being on-PCB. And as I already pointed out, they did use the same GPU architecture seen in Fury in non-HBM cards.
A good analogy would be with Athlon 64 and it's integrated memory controller in 2003. The memory controller ONLY supported DDR memory. AMD finally changed this with Phenom (maybe?) when they started integrating DDR2 controllers.
That's because of the IMC design for a specific CPU (and its associated motherboard), not because the CPU u-arch was only capable of working with a certain memory type. See Haswell (DDR3) vs Haswell-E (DDR4). Same u-arch, different memory support.
Coming back to my original post, Vega chips were inherently build with HBM2 in mind. They have a crazy 2048-bit bus to accommodate it. If AMD was planning to integrated Vega into Ryzen to make an APU, don't they have to tear out the HBM2 parts of the chip to make it work with DDR4 system ram?
Now that I've slept on it, I think what will happen is they'll have to make a new chip based loosely on Vega's architectural improvements but with full support for system memory. They've had to do that up until now with GDDR5 graphics cards.
I didn't realize anyone thought they were actually going to throw a Vega56/64 die into an APU. I usually see it stated as "Vega cores" or something, meaning the same u-arch as Vega56/64, but not the same actual chip.
So yeah, they'll be designing a new chip with the GPU portion using the same (or similar) u-arch as Vega56/64, but with a different memory subsystem.
TJ HOOKER:
I fully expect the new APU for desktop (AM4) will be the same idea as they had for APU's already. A Ryzen CPU + VEGA cores. The amount of GPU and CPU cores will vary like normal, with the BEST APU being a very light gaming chip.
Vega may have a memory controller designed for HBM memory, but the APU would be designed for a shared DDR4 memory instead. (and of course we'll get laptops and people building desktops that don't realize how much DDR4 memory bandwidth you need to avoid bottlenecking the APU).
OTHER:
back to the ARTICLE, the die shrink should reduce the power and thus temperature so that would be very important especially for VEGA64 which runs too hot and often THROTTLES down.
I'm sure POWER is first and foremost on their minds in the die shrink (while also keeping a high frequency, but it's better to optimize for reduced power at the same maximum frequency)
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