News AMD updates 3D V-Cache optimizer driver ahead of Ryzen 9000X3D launch

[Admin]

AMD appears to have updated its 3D V-Cache driver for Ryzen 9000X3D.

AMD updates 3D V-Cache optimizer driver ahead of Ryzen 9000X3D launch : Read more

 

[usertests]

AMD has already confirmed that 3D V-Cache-enabled Ryzen 9000 processors are in the works, and it is bringing some "cool" innovations to the 3D V-Cache technology itself.

I ask again, what do we think these could be? AFAIK the only thing that improved between 1st and 2nd gen V-Cache was it increased bandwidth by 25% to 2.5 TB/s.

Put a second layer of cache on the cache chiplet, same 64 MiB capacity per layer and 32 MiB at the base, and you have 160 MiB on a CCD.

 

[Deleted member 2731765]

AMD appears to have updated its 3D V-Cache driver for Ryzen 9000X3D.

Please. Nowhere it mentions these drivers are for the upcoming Ryzen 9000X3D parts. So STOP making such vague claims without any proof or backup.

Even the vanilla Ryzen 9000 series SKUs have not even launched, so it makes little sense for AMD to update it's drivers for the X3D parts, which don't even have a release date finalized yet.

 

[Deleted member 2731765]

These drivers are just a re-release of the previous version of the same AMD chipset drivers, because there was a bug in the previous release, as noted just recently by Chiphell and Benchlife forum members.

Instead of releasing a separate X3D driver, this time AMD has now bundled the whole driver package instead. Nothing new here.

 

[The Historical Fidelity]

I doubt a 6nm process would allow increased sram density for the 3D cache chiplet. For example, 7nm sram bit cell size is 0.0262um^2, 6nm = same. Of course 5nm bit cell size is 0.021um^2 so could allow for increased cache density on the v-cache chiplet.

 

[Makaveli]

i'm not expecting anything different but installing these now.

 

[usertests]

I doubt a 6nm process would allow increased sram density for the 3D cache chiplet. For example, 7nm sram bit cell size is 0.0262um^2, 6nm = same. Of course 5nm bit cell size is 0.021um^2 so could allow for increased cache density on the v-cache chiplet.

It could reduce power draw a little.

I don't think TSMC is charging AMD more for N6 than N7, since all production should eventually end up on N6. So it could just happen even if the benefits are slight.

 

[The Historical Fidelity]

It could reduce power draw a little.

I don't think TSMC is charging AMD more for N6 than N7, since all production should eventually end up on N6. So it could just happen even if the benefits are slight.

Never said they wouldn’t use N6, simply refuting the article insinuating a cache size increase from using N6.

 

[Eternalighty]

Why does the 58003dx not need this driver but 7000 series does? (I'm on the 58003dx)