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AMD x86 cores come with integrated graphics
Posted: 13 Nov 2009
Rivals AMD and Intel are both racing to deliver 32nm processors with integrated graphics. Neither company has described the cores they will use, leaving open questions about who will win or lose in the first generation merged products.
How the programming model evolves for such mixed multicore processors will be key. AMD dropped hints it is quietly lobbying for a new approach it thinks could give its chips a strategic advantage.
On the hardware side, Bobcat is a synthesisable, low-power x86 core AMD will pit against Intel's custom Atom design. Bobcat could deliver about 90 per cent of the performance of today's Atom chips at half their size, AMD said.
Bobcat has an out-of-order execution pipeline, capable of issuing two-instructions per clock cycle and—unlike Atom—sports aggressive branch prediction. The first versions of the core will consume about 2W max, but be capable of running at less than a 1W.
Bulldozer is a high performance core that merges an optimised set of the functions of two x86 cores into a single silicon block. It has two separate integer units with separate L1 and L2 caches, but the cores share a common L3 cache and an enhanced floating point unit.
The floating point unit includes two 128bit multiply-accumulate (FMAC) units. "That is the most commonly used instruction in a floating point unit and this is the first x86 to have dedicated hardware for it," said Chuck Moore, an AMD fellow who started the Bulldozer design team about three years ago.
Bulldozer is a full custom design, optimised for maximum data rates at a given power consumption level. First parts using it will be desktop and server CPUs made in a 32nm silicon-on-insulator process supporting high-K metal gates.
Both new cores support the full x86 instruction set. Bulldozer adds new extensions for its FMAC.
x86 core on 32nm
One of AMD's first Fusion processors—called Llano—will use neither Bobcat nor Bulldozer but an enhanced version of an existing 45nm x86 core moved to a 32nm process. Llano will sport four x86 cores and a graphics core capable of handling Microsoft's DirectX 11 applications programming interface all linked to DDR3 DRAM.
Moore suggested the Llano chips will come in versions using at least two different graphics cores, an option other integrated parts are likely to offer.
A separate design called Ontario will use two Bobcat cores, a DX11 GPU and DDR3 memory. However, AMD is not revealing in what process it is making the chip which is aimed at thin and light notebooks and netbooks.
Both chips will ship in volume in 2011 along with Zambezi, high-end desktop chips using four to eight of the Bulldozer cores, but no integrated graphics. Bulldozer will also show up in two server processors in 2011.
AMD is creating a design flow that merges elements of its x86 custom flow with elements of its graphics design flow which uses arrays of simpler synthesisable cores. It intends to use the merged flow to spit out new integrated designs every 12 months using different sets of cores.
"We will have the best accelerated processors every single year," said Rick Bergman, general manager of AMD's products group.
Intel is already sampling Westmere, a processor that puts in a single package a 32nm multicore Nehalem chip and a 45nm graphics chip. It plans to have a fully integrated chip in 2011 using its SandyBridge x86 core and graphics, likely arriving about the same time as AMD's Fusion parts.
Bergman and others confirmed AMD has working silicon of it least one of its Fusion parts, likely the Llano design. Multiple 32nm Fusion parts will sample to OEMs before June and ramp to volume in the second half of 2010.
AMD edge
Intel is ahead in process technology and doesn't face AMD's financial challenges as the two compete with roughly similar architectures. AMD executives referred to a still-evolving programming model for its integrated chips as a strategic differentiator.
"Fusion is not just CPU and graphics on the same die," said Dirk Meyer, CEO of AMD, speaking at an annual analysts meeting here. "The vision is to enable new data-parallel applications to run on the most power-efficient core possible, and that's where our vision differs from Intel's," he said.
Intel hasn't discussed its plans in detail. However, observers expect it will evolve from using versions of its existing integrated graphics cores to using Larrabee, a GPU based on an array of new x86 cores. Such merged CPUs could handle graphics with only modest changes to today's operating systems, languages and programming tools.
AMD is pushing for a more dramatic shift. Initially it will use today's OpenCL and Microsoft DirectCompute APIs to let CPUs manage and offload tasks to GPUs as needed.
"I believe there is a level of programmability above [that]," said Moore.
Specifically, AMD wants to see GPUs become full citizens, equal to CPUs, in future OS, languages and tools. That scenario requires four or five significant technology shifts, but the pay off could be worthwhile.
The resulting programming model would eliminate the need for separate x86 and graphics memory partitions. It would also let the operating system elevate the GPU from its role as a peripheral accessed by drivers, letting software more directly tap graphics hardware capabilities.
Bringing the GPU into the host processor's cache coherent domain is one of the challenges to enabling that vision. AMD has plans that could simplify that effort.
Moore suggested future Fusion processors will more closely merge x86 and SIMD graphics capabilities in a way similar to how Bulldozer mergers the best of two x86 cores into one core design.
In the end, "there is more of a programming model challenge for us [than Intel] to extend the GPU, but there's an order of magnitude difference in the experience we are going for," Moore said.
Tech, financial roadblocks
AMD also faces a process technology challenge.
"Historically, we have been in a zone of 6-12 months from the leading edge technology," said Meyer. "We are on the edge of that with the 32nm transition, and want to be more in the middle of it with the 22nm transition," he added.
Indeed, AMD's main source, GlobalFoundries will not have production availability of 32nm technology until the second half of 2010. AMD may have had to turn to graphics foundry partner TSMC for a low power version of a 32nm processor for its Ontario chips. That's a capability it appears GlobalFoundries may leapfrog as it quick steps from a 45nm to a 28nm node.
On the financial front, AMD is trying to manage a heavy load of debt, maintain a reasonable minimum of cash on hand and get back to profitability. The company's new chief financial officer, Thomas Seifert, could not promise analysts here AMD will be in the black for its next two quarters.
"We will work hard to keep our nose above water, but it's too early to tell how the [PC market] seasonal downturn will impact us," Seifert said.
To keep profit margins up, AMD hopes to shave the per cent of sales spent on R&D from about 23 to no more than 19 per cent. It hopes to see those savings by 2011, once much of the hard work of transitioning to a new hybrid CPU/GPU processor development methodology is finished.
- Rick Merritt
EE Times
Posted: 13 Nov 2009
Rivals AMD and Intel are both racing to deliver 32nm processors with integrated graphics. Neither company has described the cores they will use, leaving open questions about who will win or lose in the first generation merged products.
How the programming model evolves for such mixed multicore processors will be key. AMD dropped hints it is quietly lobbying for a new approach it thinks could give its chips a strategic advantage.
On the hardware side, Bobcat is a synthesisable, low-power x86 core AMD will pit against Intel's custom Atom design. Bobcat could deliver about 90 per cent of the performance of today's Atom chips at half their size, AMD said.
Bobcat has an out-of-order execution pipeline, capable of issuing two-instructions per clock cycle and—unlike Atom—sports aggressive branch prediction. The first versions of the core will consume about 2W max, but be capable of running at less than a 1W.
Bulldozer is a high performance core that merges an optimised set of the functions of two x86 cores into a single silicon block. It has two separate integer units with separate L1 and L2 caches, but the cores share a common L3 cache and an enhanced floating point unit.
The floating point unit includes two 128bit multiply-accumulate (FMAC) units. "That is the most commonly used instruction in a floating point unit and this is the first x86 to have dedicated hardware for it," said Chuck Moore, an AMD fellow who started the Bulldozer design team about three years ago.
Bulldozer is a full custom design, optimised for maximum data rates at a given power consumption level. First parts using it will be desktop and server CPUs made in a 32nm silicon-on-insulator process supporting high-K metal gates.
Both new cores support the full x86 instruction set. Bulldozer adds new extensions for its FMAC.
x86 core on 32nm
One of AMD's first Fusion processors—called Llano—will use neither Bobcat nor Bulldozer but an enhanced version of an existing 45nm x86 core moved to a 32nm process. Llano will sport four x86 cores and a graphics core capable of handling Microsoft's DirectX 11 applications programming interface all linked to DDR3 DRAM.
Moore suggested the Llano chips will come in versions using at least two different graphics cores, an option other integrated parts are likely to offer.
A separate design called Ontario will use two Bobcat cores, a DX11 GPU and DDR3 memory. However, AMD is not revealing in what process it is making the chip which is aimed at thin and light notebooks and netbooks.
Both chips will ship in volume in 2011 along with Zambezi, high-end desktop chips using four to eight of the Bulldozer cores, but no integrated graphics. Bulldozer will also show up in two server processors in 2011.
AMD is creating a design flow that merges elements of its x86 custom flow with elements of its graphics design flow which uses arrays of simpler synthesisable cores. It intends to use the merged flow to spit out new integrated designs every 12 months using different sets of cores.
"We will have the best accelerated processors every single year," said Rick Bergman, general manager of AMD's products group.
Intel is already sampling Westmere, a processor that puts in a single package a 32nm multicore Nehalem chip and a 45nm graphics chip. It plans to have a fully integrated chip in 2011 using its SandyBridge x86 core and graphics, likely arriving about the same time as AMD's Fusion parts.
Bergman and others confirmed AMD has working silicon of it least one of its Fusion parts, likely the Llano design. Multiple 32nm Fusion parts will sample to OEMs before June and ramp to volume in the second half of 2010.
AMD edge
Intel is ahead in process technology and doesn't face AMD's financial challenges as the two compete with roughly similar architectures. AMD executives referred to a still-evolving programming model for its integrated chips as a strategic differentiator.
"Fusion is not just CPU and graphics on the same die," said Dirk Meyer, CEO of AMD, speaking at an annual analysts meeting here. "The vision is to enable new data-parallel applications to run on the most power-efficient core possible, and that's where our vision differs from Intel's," he said.
Intel hasn't discussed its plans in detail. However, observers expect it will evolve from using versions of its existing integrated graphics cores to using Larrabee, a GPU based on an array of new x86 cores. Such merged CPUs could handle graphics with only modest changes to today's operating systems, languages and programming tools.
AMD is pushing for a more dramatic shift. Initially it will use today's OpenCL and Microsoft DirectCompute APIs to let CPUs manage and offload tasks to GPUs as needed.
"I believe there is a level of programmability above [that]," said Moore.
Specifically, AMD wants to see GPUs become full citizens, equal to CPUs, in future OS, languages and tools. That scenario requires four or five significant technology shifts, but the pay off could be worthwhile.
The resulting programming model would eliminate the need for separate x86 and graphics memory partitions. It would also let the operating system elevate the GPU from its role as a peripheral accessed by drivers, letting software more directly tap graphics hardware capabilities.
Bringing the GPU into the host processor's cache coherent domain is one of the challenges to enabling that vision. AMD has plans that could simplify that effort.
Moore suggested future Fusion processors will more closely merge x86 and SIMD graphics capabilities in a way similar to how Bulldozer mergers the best of two x86 cores into one core design.
In the end, "there is more of a programming model challenge for us [than Intel] to extend the GPU, but there's an order of magnitude difference in the experience we are going for," Moore said.
Tech, financial roadblocks
AMD also faces a process technology challenge.
"Historically, we have been in a zone of 6-12 months from the leading edge technology," said Meyer. "We are on the edge of that with the 32nm transition, and want to be more in the middle of it with the 22nm transition," he added.
Indeed, AMD's main source, GlobalFoundries will not have production availability of 32nm technology until the second half of 2010. AMD may have had to turn to graphics foundry partner TSMC for a low power version of a 32nm processor for its Ontario chips. That's a capability it appears GlobalFoundries may leapfrog as it quick steps from a 45nm to a 28nm node.
On the financial front, AMD is trying to manage a heavy load of debt, maintain a reasonable minimum of cash on hand and get back to profitability. The company's new chief financial officer, Thomas Seifert, could not promise analysts here AMD will be in the black for its next two quarters.
"We will work hard to keep our nose above water, but it's too early to tell how the [PC market] seasonal downturn will impact us," Seifert said.
To keep profit margins up, AMD hopes to shave the per cent of sales spent on R&D from about 23 to no more than 19 per cent. It hopes to see those savings by 2011, once much of the hard work of transitioning to a new hybrid CPU/GPU processor development methodology is finished.
- Rick Merritt
EE Times
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