News AMD's EPYC 'Bergamo' and Zen 4c Detailed: Same as Zen 4, But Denser

[Admin]

AMD's Zen 4c retains the same logic design as Zen 4c, but it is implemented differently, allowing for higher core count.

AMD's EPYC 'Bergamo' and Zen 4c Detailed: Same as Zen 4, But Denser : Read more

 

[Deleted member 2731765]

AMD's EPYC 'Bergamo' processor packs 128 cores and sits in the same Socket SP5 as the 96-core EPYC 'Genoa' CPU

Because it is drop-in compatible with the existing SP5 socket with no software port required since the same Zen 4 ISA is used.

So, AMD also managed to fit twice the number of cores and threads with the same L3 cache within a die size that's under 10% bigger than the Zen 4 CCD (72.7mm2 vs 66.3mm2).

Considering that AMD used a 8 CCD package for its EPYC Bergamo CPUs, it might be possible we get a 12 CCD package in future as well, which could offer up to 192 cores and 384 threads.

 

[bit_user]

Could this possibly be the same core they used on Phoenix? Is there any chance that Bergamo uses the same N4 process for its CCDs?

Or, maybe Phoenix didn't go that route due to the impact on single-thread performance.

 

[-Fran-]

The real question here is if that I/O die* is pink.

Regards.

 

[bit_user]

The real question here is if that I/O die* is pink.

Huh?

 

[TJ Hooker]

Could this possibly be the same core they used on Phoenix? Is there any chance that Bergamo uses the same N4 process for its CCDs?

Or, maybe Phoenix didn't go that route due to the impact on single-thread performance.

Yes, Phoenix uses Zen4c, at least according to the semianalysis article referenced in this article.

 

[Deleted member 2731765]

Here is the exact core breakdown: So just 4 partitions (L2, Front End, Execution, FPU) now with Zen4C.

Could this possibly be the same core they used on Phoenix? Is there any chance that Bergamo uses the same N4 process for its CCDs?

Or, maybe Phoenix didn't go that route due to the impact on single-thread performance.

Nah the original Phoenix doesn't use the exact same core design, but the upcoming Phoenix 2 does, using AMD's hybrid Big.Little-like design.

Codenamed Phoenix 2, this SKU will leverage a 2+4 design with two P-cores and four E-cores. The former refers to the standard Zen 4 cores used on the Ryzen 7000 processors, while the latter is internally known as the “classic dense core”.

But phoenix uses the dense core in the context of "Efficiency” cores, whereas Bergamo is actually using a denser core variant of Zen 4c, slightly different from phoenix 2's E-core if past documents and rumors are to be believed.

Phoenix has a variant that use "big-LITTLE" like core design, which contains a CCX with 2+4 design with standard Zen 4 and a dense-optimized variant of Zen 4 (Zen 4c/Zen 4 Dense).

Zen 4C and Zen 4 could be more alike than Intel’s Performance and Efficiency cores. It seems for the half size Zen4c AMD is sacrificing just the half of L3 and some frequency. Zen 4 core is also about double the physical size of a Zen 4C core, while Intel’s P-core is approximately 3.5 times larger than its E-core.

AMD’s strategy of maintaining two mostly similar cores could prove advantageous.

Size ratio, AMD ~2:1.

Intel ~3.5:1.

 

[qwertymac93]

Huh?

The codename of the I/O die is "Floyd". A pink I/O die would be "Pink Floyd".
Har har.

 

[usertests]

This is the specific kind of information I wanted to know about Zen 4c density other than L3 reduction, although some of it is still speculation for now. Looks good.

 

[TJ Hooker]

On the microarchitecture level, Zen 4c retains the same design as Zen 4, including identical features and instructions-per-clock-performance [...]

Is it realistic for zen 4c have the same IPC as zen 4, despite having half the L3 per core/per CCX, and apparently slower cache overall (due to condensed SRAM cell structure)?

Edit: And that assumes that cache structure really is the only thing that's functionally changed.

 

[bit_user]

Is it realistic for zen 4c have the same IPC as zen 4, despite having half the L3 per core/per CCX, and apparently slower cache overall (due to condensed SRAM cell structure)?

In the Semi-Analysis table @Metal Messiah. posted, the L2 cells didn't shrink. If it's just L3, and if their latency increased proportional to the longer clock tick, then the software-visible latency would be the same and your only concern would be the smaller capacity.

Just a hypothetical, but reducing software-visible latencies is one of the nice things about lowering clock speed. Energy-efficiency is another.

I'm definitely intrigued by AMD's approach. In future generations, I think they can't help but tweak other aspects of the microarchitecture, since the parameters optimized for high-speed cores will no longer be optimal for lower-speed ones. Not to mention area- and power- efficiency.

 

[TerryLaze]

Phoenix has a variant that use "big-LITTLE" like core design, which contains a CCX with 2+4 design with standard Zen 4 and a dense-optimized variant of Zen 4 (Zen 4c/Zen 4 Dense).

Zen 4C and Zen 4 could be more alike than Intel’s Performance and Efficiency cores. It seems for the half size Zen4c AMD is sacrificing just the half of L3 and some frequency. Zen 4 core is also about double the physical size of a Zen 4C core, while Intel’s P-core is approximately 3.5 times larger than its E-core.

AMD’s strategy of maintaining two mostly similar cores could prove advantageous.

Size ratio, AMD ~2:1.

Intel ~3.5:1.

How is a die shrink anywhere close to what intel did?
Intel's p-cores are 3.5 times larger because the e-cores have so many fewer elements.
How are the 4C cores supposed to use less power? I guess because they are running at lower clocks but I also guess that that is only because they are so tightly packed that you can't cool them enough for them to run higher clocks.

The x3d chips use less power because they have more cache, the 4C cores will have less cache so how will they be saving power?

The 4C cores are going to add heat to the normal cores while the e-cores act like dark silicon and take at least some heat away from the main cores.

Zen 4 is already barely coolable, AMD better have a plan to make cooling easier.
Good luck to the server customers that will have to cool the same 400W at double the thermal density...

But it is great for AMD because it allows them to make more CPUs from the same amount of waffers.

 

[bit_user]

How is a die shrink anywhere close to what intel did?
Intel's p-cores are 3.5 times larger because the e-cores have so many fewer elements.
How are the 4C cores supposed to use less power? I guess because they are running at lower clocks but I also guess that that is only because they are so tightly packed that you can't cool them enough for them to run higher clocks.

The x3d chips use less power because they have more cache, the 4C cores will have less cache so how will they be saving power?

The 4C cores are going to add heat to the normal cores while the e-cores act like dark silicon and take at least some heat away from the main cores.

Zen 4 is already barely coolable, AMD better have a plan to make cooling easier.
Good luck to the server customers that will have to cool the same 400W at double the thermal density...

But it is great for AMD because it allows them to make more CPUs from the same amount of waffers.

So much FUD. Let's just wait and see how it benchmarks.

 

[TerryLaze]

So much FUD. Let's just wait and see how it benchmarks.

If it's half the size and uses the same power, you know the things the article actually said, then nothing I said is FUD.
Each core is only going to get half the heat wicked away compared to previous cores that's just physics it can't work any other way.
The FUD or no FUD comes in with this, AMD better have a plan to make cooling easier.
There was no mentioning of AMD changing anything that has to do with the heatsink or anything else that would help with the cooling.

 

[bit_user]

Each core is only going to get half the heat wicked away compared to previous cores that's just physics it can't work any other way.

You don't know the thermal density, but given that they're targeting the same power envelope as Genoa with slightly larger chiplets suggests it's going to be roughly the same.

There was no mentioning of AMD changing anything that has to do with the heatsink or anything else that would help with the cooling.

You're comparing unrelated products. This article concerns server CPUs, not desktop AM5-socketed ones. And if we're talking laptop CPUs, again your references to AM5 are off-base.

So, I stand by what I said. You're trying to throw FUD all over this.

 

[Elusive Ruse]

You don't know the thermal density, but given that they're targeting the same power envelope as Genoa with slightly larger chiplets suggests it's going to be roughly the same.


You're comparing unrelated products. This article concerns server CPUs, not desktop AM5-socketed ones. And if we're talking laptop CPUs, again your references to AM5 are off-base.

So, I stand by what I said. You're trying to throw FUD all over this.

He is an Intel employee, a forum plant, that's his job.

 

[TJ Hooker]

In the Semi-Analysis table @Metal Messiah. posted, the L2 cells didn't shrink. If it's just L3, and if their latency increased proportional to the longer clock tick, then the software-visible latency would be the same and your only concern would be the smaller capacity.

Just a hypothetical, but reducing software-visible latencies is one of the nice things about lowering clock speed. Energy-efficiency is another.

I'm definitely intrigued by AMD's approach. In future generations, I think they can't help but tweak other aspects of the microarchitecture, since the parameters optimized for high-speed cores will no longer be optimal for lower-speed ones. Not to mention area- and power- efficiency.

The table does say core SRAM area (excluding L2) shrank significantly though. I'm assuming they're not including L3 in that figure, so I guess L1 and register SRAM shrunk (and therefore potentially got slower) as well? I have no idea how/if that would impact performance, maybe it would also be largely hidden by the lower clock speeds as you mentioned.

(And by "shrunk" I mean going from 8T dual port cells to 6T pseudo-dual-port cells, as the article describes)

 

[bit_user]

The table does say core SRAM area (excluding L2) shrank significantly though. I'm assuming they're not including L3 in that figure, so I guess L1 and register SRAM shrunk (and therefore potentially got slower) as well?

(And by "shrunk" I mean going from 8T dual port cells to 6T pseudo-dual-port cells, as the article describes)

It's a good question. Registers can't afford to get slower than the inverse in peak clock speed, though. That would destroy its IPC.

 

[NinoPino]

Huh?

How is a die shrink anywhere close to what intel did?
Intel's p-cores are 3.5 times larger because the e-cores have so many fewer elements.
How are the 4C cores supposed to use less power? I guess because they are running at lower clocks but I also guess that that is only because they are so tightly packed that you can't cool them enough for them to run higher clocks.

Speed reduction and power are not linearly connected, so may be a little clock reduction lead to a big power reduction. In case of 4c, not needing to reach high speed may permit the use of more energy efficent silicon libraries (imho of course).

The x3d chips use less power because they have more cache, the 4C cores will have less cache so how will they be saving power?

I agree with you. This is an interesting argument to explore.

Zen 4 is already barely coolable, AMD better have a plan to make cooling easier.

No need. Zen 4 is already efficient (at least comparing to Intel's), 4c is more efficient, so I dont see a problem here.

Good luck to the server customers that will have to cool the same 400W at double the thermal density...

The thermal density is watt/die area, so I think there is no significant difference in thermal density of 96 zen 4 vs 128 zen 4c processors.

But it is great for AMD because it allows them to make more CPUs from the same amount of waffers.

More cores.

 

[AkroZ]

The real question here is if that I/O die* is pink.

Regards.

Huh?

The codename of the I/O die is "Floyd". A pink I/O die would be "Pink Floyd".
Har har.

This would not be the first time.

 

[TerryLaze]

No need. Zen 4 is already efficient (at least comparing to Intel's), 4c is more efficient, so I dont see a problem here.

Efficiency has nothing much to do with how well you can cool it.
With very expensive cooling, the 7950x using 215W (zero above stock) hits 95 degrees while the 13900k using 330W (30% above stock) reaches 86 degrees.

A Lighter Touch: Exploring CPU Power Scaling On Core i9-13900K and Ryzen 9 7950X

www.anandtech.com

The thermal density is watt/die area, so I think there is no significant difference in thermal density of 96 zen 4 vs 128 zen 4c processors.

Cooling the whole CPU isn't the thing I talked about, each single core also has an watt/area so with the same amount of cooling the core would be getting hotter, unless the decrease in clocks levels that out.

 

[bit_user]

Efficiency has nothing much to do with how well you can cool it.

Nobody else is talking about cooling, Terry. I've already pointed out that the article doesn't involve AM5, desktop processors are off-topic.

Cooling the whole CPU isn't the thing I talked about, each single core also has an watt/area so with the same amount of cooling the core would be getting hotter, unless the decrease in clocks levels that out.

Yes, that was answered in the article. It said the CPUs will target the same power envelope, which necessarily means each core will use less power. From the sound of it, the chiplets will be a little bigger, which should further reduce the thermal density, at the die level.

 

[TerryLaze]

Nobody else is talking about cooling, Terry. I've already pointed out that the article doesn't involve AM5, desktop processors are off-topic.

Nino made the claim that efficiency has somehow something to do with cooling and that example shows that it doesn't.

 

[-Fran-]

Nino made the claim that efficiency has somehow something to do with cooling and that example shows that it doesn't.

Strictly speaking temperature does affect efficiency in any conductive material. I guess the question is: does it really matter at this power and temperature envelope for these materials. I guess the answer would be "not that much".

Regards.

 

[bit_user]

Nino made the claim that efficiency has somehow something to do with cooling and that example shows that it doesn't.

No, Nino didn't.

Strictly speaking temperature does affect efficiency in any conductive material.

It's irrelevant, because the article says it uses the same power envelope and packaging as Genoa. Therefore, temperatures should be similar.

Please don't legitimize Terry's attempts to thread-jack.