AMD's Future Chips & SoC's: News, Info & Rumours.

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The main bottleneck in game loading time is insufficient parallelism in the loading process to leverage SSD bandwidth, IOPS and extra CPU cores.
HD reads, be it from a HDD or SSD, are still a serial operation in nature; there's nothing to make parallel. No matter how much CPU resources you throw it at, you are still limited by Read/Write bandwidth [and to a less extent memory bandwidth].
 
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HD reads, be it from a HDD or SSD, are still a serial operation in nature
The data transfer over the serial interface may be serial but an SSD has multiple channels to NAND chips that allow it to work on multiple concurrent IOs when said IOs hit different channels to achieve much higher overall throughput and lower overall latency. On HDDs, queuing multiple read/write commands allows the drive controller to re-order them in the most efficient order.

Most games start loading a chunk of data from storage during which the CPU has nothing to do, then unpacks it where often only one CPU core works on and no storage IO is happening. Tons of wasted CPU and IO time there.
 
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It's with the same caveat though. Still good IMO, but I can't deny I'll be scared if I swap my 2700X for a pontential 4700X and it doesn't boot on the firs try xD

Cheers!
You will just need to have a plan ready incase you need to roll back to an earlier BIOS version.
AMD and Asus both said that I couldn't roll back my B450-F BIOS once I flashed a BIOS that had Ryzen 3000 support.
But there is a way to do it using AFUDOS and the older BIOS on a Bootable USB stick.
So I'm pretty confident that will be the case for the 4000 Series BIOS as well (at least for my Asus MBs).
 
To be honest it all makes sense - and I think AMD's response here is sensible and fair - they were after all selling B450 motherboards as the entry level option for Ryzen 3000 series.

It sucks a bit for me as I have two machines based on 300 series chipset boards, however on the flip side, I've already got the option to upgrade to a 12 or 16 core 3000 series cpu on both motherboards so much of an issue really.
 
To be honest it all makes sense - and I think AMD's response here is sensible and fair - they were after all selling B450 motherboards as the entry level option for Ryzen 3000 series.

It sucks a bit for me as I have two machines based on 300 series chipset boards, however on the flip side, I've already got the option to upgrade to a 12 or 16 core 3000 series cpu on both motherboards so much of an issue really.
I am not a AMD fanboy or something but at least they listen to their customers concerns and tries to find a work around, you have to give them that. Then again much of this could have been avoided if they would have released b550 on time.
 
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As usual CoreTeks sounds very knowledgeable but he repeatedly gets things totally wrong. He even says in this video that everything he's talking about is a guess based on the fact the new cooler design has a fan on the back and the PCB looks fairly short.

It's a nice idea - it would be interesting if he is correct, however I'm not convinced. There's no leaks or anything pointing to the 3000 series including a second accelerator chip (which would be massive news) - and nVidia have bumped up the die size for this series quite a bit vs previous gens, I doubt they would need to do so with a big node shrink if they have moved most of the RTX hardware off onto a separate chip.

If this is true (that the new gen is a larger, 7nm die + a second large co-processor) then you can expect the price on these new cards to go up significantly from the current gen. nVidia never give their silicone away for cheap.
 
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As usual CoreTeks sounds very knowledgeable but he repeatedly gets things totally wrong. He even says in this video that everything he's talking about is a guess based on the fact the new cooler design has a fan on the back and the PCB looks fairly short.

It's a nice idea - it would be interesting if he is correct, however I'm not convinced. There's no leaks or anything pointing to the 3000 series including a second accelerator chip (which would be massive news) - and nVidia have bumped up the die size for this series quite a bit vs previous gens, I doubt they would need to do so with a big node shrink if they have moved most of the RTX hardware off onto a separate chip.

If this is true (that the new gen is a larger, 7nm die + a second large co-processor) then you can expect the price on these new cards to go up significantly from the current gen. nVidia never give their silicone away for cheap.
I know m8 it's a fascinating idea if there not doing it maybe they should be an AMD may look at a similar solution down the road... the GPU chip would be a lot smaller actually without all those extra transistors right an faster an cooler...if it turns out to be true it could put the AMD's console contracts with MS an Sony in jeopardy in the future...I wonder is this why Lisa recently got in bed with Nvidia on that deal.. can't seam to stop thinking about it...

A dedicated chip for a dedicated task is always better in my experience... and reducing the size of that previously "huge" RTX die is gonna make for some serious clock frequency increase as well.. So it could have a GPU that runs a hell of a lot faster than the Previous RTX gen... and then a small or similar sized second chip which is tailored to light-maps & texture compression... connected with NVlink and they do have previous experience in syncing chips working on same workloads etc... both with PhisX and also with SLi the tech they purchased off 3dfx way back when when they put them out of business an bought there IP.
It also gives them the added benefit of reducing cost at TSMC on the cutting edge node (with a smaller chip better yields an most off all less heat an faster clock speeds) and at the same time fabbing the other chip on a cheaper process at Samsung... sounds genius.
I tell if it is possible an they are not doing it they should be... also AMD may look at a similar solution down the road in my opinion. If this works for Nvidia they will have succeeded in preventing the GPU from being pulled into the SoC... an keeps the need for very high end discrete graphics cards... which remember was Jensens goal... when he increased the transistor count an went with Raytracing in the first place, as I say so that the GPU couldn't be pulled into the SoC...but the RTX chip was way too big an hot and slow.. this may theoretically solve all of those problems...
Remeber we used to have a 2d card an up to two separate 3d cards all working together.. an a separate discrete 3d positional audio card for sound... I don't think will be any problem in splitting up the workloads between different hardware chips.. there never has been in the past..
Well we are living in the age of parallel and Asynchronous compute right so why the hell not is my question, were breaking up workloads an executing simultaneously in real time all over the place why not do the same here it does seam like the way forward no ?


Edit: You know what maybe they are jus cooling one massive die, but what an idea, can it be done, I have more of the feeling of why not or why isn't being done maybe that's actually the better question right .. the mind boggles. What an idea, I know he's guessing but fair play to him for throwing that out there with fear of ridicule etc... I don't know I am not technical enough to know that it is possible (not even close) but I can say I'd kinda be more surprised if it was not possible... Were in the age of Heterogeneous compute right. Sounds like it may be the next logical step, this is what it's all about. AMD have been talking about SoC with CPU's GPU's and tailored ASIC's for ages now... with workloads being thrown at the silicone engineered and best suited to execute it.
 
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I know m8 it's a fascinating idea if there not doing it maybe they should be an AMD may look at a similar solution down the road... the GPU chip would be a lot smaller actually without all those extra transistors right an faster an cooler...if it turns out to be true it could put the AMD's console contracts with MS an Sony in jeopardy in the future...I wonder is this why Lisa recently got in bed with Nvidia on that deal.. can't seam to stop thinking about it...

A dedicated chip for a dedicated task is always better in my experience... and reducing the size of that previously "huge" RTX die is gonna make for some serious clock frequency increase as well.. So it could have a GPU that runs a hell of a lot faster than the Previous RTX gen... and then a small or similar sized second chip which is tailored to light-maps & texture compression... connected with NVlink and they do have previous experience in syncing chips working on same workloads etc... both with PhisX and also with SLi the tech they purchased off 3dfx way back when when they put them out of business an bought there IP.
It also gives them the added benefit of reducing cost at TSMC on the cutting edge node (with a smaller chip better yields an most off all less heat an faster clock speeds) and at the same time fabbing the other chip on a cheaper process at Samsung... sounds genius.
I tell if it is possible an they are not doing it they should be... also AMD may look at a similar solution down the road in my opinion. If this works for Nvidia they will have succeeded in preventing the GPU from being pulled into the SoC... an keeps the need for very high end discrete graphics cards... which remember was Jensens goal... when he increased the transistor count an went with Raytracing in the first place, as I say so that the GPU couldn't be pulled into the SoC...but the RTX chip was way too big an hot and slow.. this may theoretically solve all of those problems...
Remeber we used to have a 2d card an up to two separate 3d cards all working together.. an a separate discrete 3d positional audio card for sound... I don't think will be any problem in splitting up the workloads between different hardware chips.. there never has been in the past..
Well we are living in the age of parallel and Asynchronous compute right so why the hell not is my question, were breaking up workloads an executing simultaneously in real time all over the place why not do the same here it does seam like the way forward no ?


Edit: You know what maybe they are jus cooling one massive die, but what an idea, can it be done, I have more of the feeling of why not or why isn't being done maybe that's actually the better question right .. the mind boggles. What an idea, I know he's guessing but fair play to him for throwing that out there with fear of ridicule etc... I don't know I am not technical enough to know that it is possible (not even close) but I can say I'd kinda be more surprised if it was not possible... Were in the age of Heterogeneous compute right. Sounds like it may be the next logical step, this is what it's all about. AMD have been talking about SoC with CPU's GPU's and tailored ASIC's for ages now... with workloads being thrown at the silicone engineered and best suited to execute it.
This has been a topic of much debate over the years... the first graphics accelerators used multiple chips for different parts of the pipeline, and even a separate card for 2D in the case of the early Voodoo cards as you mention...

Switching from a monolithic chip to chiplets has worked out well for AMD on the cpu side, although it has been noted that the 8 cores in a single die for Renoir perform comparatively better than the 2 x 4 core CCD + separate IO die of desktop Ryzen, despite having much less cache - so that decision is very much a compromise. This is usually far worse in graphics, which is why multi-chip graphics cards have never worked as well as a larger single chip - mainly due to the large amounts of data involved. Whenever a large block of data has to be moved it costs both power and latency to do so - which is detrimental to graphics performance. It's not as big an issue on the cpu as often the cpu cores are working independently of each other.

I think the 'holly grail' required to allow all of this to work is to get around the inherent problem of moving data - AMD have done a lot of work on this (and I'm sure nVidia and Intel have done similar projects) - where multiple discrete chips have fully coherent shared memory - that would allow the data to remain in one place and be worked on by multiple different devices without the drawbacks. I've not heard anything to suggest this is part of Ampere though.

The other case where it might make sense is if the RTX functions can be handled truly independently of the rest of the graphics pipeline, in which case moving it off on a separate accelerator would be possible, although given it's effectively a lighting calculation I'm not sure that is the case. What I would say though is in the long run, ray tracing hardware will ultimately finish up integrated into the GPU, just like texture units, geometry setup engines, rops and so on have all done. I think any multi chip approach would be a short term stop gap solution.
 
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This has been a topic of much debate over the years... the first graphics accelerators used multiple chips for different parts of the pipeline, and even a separate card for 2D in the case of the early Voodoo cards as you mention...

Switching from a monolithic chip to chiplets has worked out well for AMD on the cpu side, although it has been noted that the 8 cores in a single die for Renoir perform comparatively better than the 2 x 4 core CCD + separate IO die of desktop Ryzen, despite having much less cache - so that decision is very much a compromise. This is usually far worse in graphics, which is why multi-chip graphics cards have never worked as well as a larger single chip - mainly due to the large amounts of data involved. Whenever a large block of data has to be moved it costs both power and latency to do so - which is detrimental to graphics performance. It's not as big an issue on the cpu as often the cpu cores are working independently of each other.

I think the 'holly grail' required to allow all of this to work is to get around the inherent problem of moving data - AMD have done a lot of work on this (and I'm sure nVidia and Intel have done similar projects) - where multiple discrete chips have fully coherent shared memory - that would allow the data to remain in one place and be worked on by multiple different devices without the drawbacks. I've not heard anything to suggest this is part of Ampere though.

The other case where it might make sense is if the RTX functions can be handled truly independently of the rest of the graphics pipeline, in which case moving it off on a separate accelerator would be possible, although given it's effectively a lighting calculation I'm not sure that is the case. What I would say though is in the long run, ray tracing hardware will ultimately finish up integrated into the GPU, just like texture units, geometry setup engines, rops and so on have all done. I think any multi chip approach would be a short term stop gap solution.
Appreciate your input, nice take on it btw.. the best response I have heard tbh.. most people jus kinda freak out an say it's not poss without backing it up with an technical reasoning.

If they could separate the Ray-Tracing workload I wouldn't be surprised if they tried something like this... as you say it may only be temp (have to agree there an hadn't occurred to me) it might pulled into the GPU in the future alright. But what about all this talk fo Heterogeneous compute and SoC's with CPU's ASIC's GPU's basically a chip for every workload, when is that happening... Because it sounds like in a world with SoC capable of that this would be the way to go no ?
 
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