News AMD's new Zen 5 flagship gets benchmarked — Ryzen 9 9950X Engineering Sample isn't as impressive in Blender at maximum power settings

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Admin said:
An AMD Ryzen 9 9950X ES gets a full suite of Blender benchmarks at different PPT/TDP targets.

AMD's new Zen 5 flagship gets benchmarked — Ryzen 9 9950X Engineering Sample isn't as impressive in Blender at maximum power settings : Read more
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It also remained fairly competitive with the 170W Ryzen 7950X at wattages as low as 120W.
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*Author's Note: My prior article on this topic referred to these power targets as "TDP" instead of "PPT". These are...mostly the same thing, but whereas TDP (Thermal Design Power) refers to the CPU's power target, PPT (Package Power Tracking) refers to all power being directed to the CPU socket, and adjustments change the maximum wattage to the socket, and thus real TDP is lower. "Unlimited PPT" allows for as much wattage as the CPU and socket can support.
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Not just the prior article...the 7950x has a TDP of 170W and a PPT of 230W.
So roughly a 30% increase in performance for the same power, not bad at all.

But apparently also no overclocking headroom at all since AMD maxed it out as much as possible already.
 
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Apparently <6 Ghz is becoming a hard limit for actual technology, very interesting to see.
They need to work hard on architectures and IPC.
 
I don't know why the 61°C should impress you, because I believe it's a programmed threshold.

If I remember correctly, Lisa Su said that Ryzens will only ever go beyond their PPT limits if your CPU won't exceed such a relatively low temperature threshold.

They'll keep clocking up to 90°C within PPT limits, but if you want to go outside, a much lower temperature needs to be maintained.

So what's impressive is perhaps more the cooler that is able to keep it at around 60°C with 250 Watts of heat.

I'd love to know if the CCDs have been maintained at similar size even with the process shrink, just to maintain enough cooling surface. I guess they've invested more transistors into IPC improvements, but they might have also added more dark silicon for the purpose of maintaining cooling capabilities at these high clocks.

I guess by doing the opposite of what they do for the compact cores, they could theoretically even reach 6GHz at the cost of a much larger CCD (which they can't fit, either). But the economic optimum is much nearer the compact cores, even if the desktop enthusiast market probably wouldn't buy that, even if it meant a max of 32 cores instead of 16.

I'd love to see a dual 12 core (4P+8C) variant benchmarked, to see where that would wind up...
And another with V-cache on the P cores...

So many possibilities, but AMD needs to keep the variants as low as possible for economy!
 
abufrejoval said:
I'd love to know if the CCDs have been maintained at similar size even with the process shrink, just to maintain enough cooling surface.
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TSMC N4 is a refinement of N5 so even if the chips were roughly the same transistor wise they aren't likely much smaller if at all. If I'm remembering the numbers correctly it's a single digit percentage density improvement over N5.
 
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SunMaster said:
Given what is happening to the higher end 13k/14k series CPUs, perhaps Intel didn't have headroom either.
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I believe the issues are purely due to mobos pushing way too much Vcore into the CPUs in an attempts to make auto clocks more stable at higher clocks.
If you tune it yourself or get a mobo that doesn't push everything to 11 from the get go you would have no issues.
Also if AMD doesn't come out pre release and forces mobo makers to use safe settings the same will happen for them, now that the node has become good enough to use high values.

Also unlimited PPT = 318W pretty much in line with what the 14th gen draws unlimited, and it shows that it's PBO which is overclocking just like all core enhancement (and all the equivalents) on intel, I wonder how the reviewers are going to spin this into a positive for amd while keeping it a negative for intel.
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TerryLaze said:
I believe the issues are purely due to mobos pushing way too much Vcore into the CPUs in an attempts to make auto clocks more stable at higher clocks.
If you tune it yourself or get a mobo that doesn't push everything to 11 from the get go you would have no issues.
Also if AMD doesn't come out pre release and forces mobo makers to use safe settings the same will happen for them, now that the node has become good enough to use high values.
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You seem to believe the motherboards are breaking them, by using far to agressive voltages. As did most people, myself included.

Looking at all the info that has been appearing the last few days I believe a great number of these CPUs are going to break by operating fully within Intel's spec. Buildzoid had a rant about it, lengthy as usual. I believe he could be onto something.
 
SunMaster said:
Buildzoid had a rant about it, lengthy as usual. I believe he could be onto something.
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Yeah but he also only goes by what very limited info that vendel and the others share, there is no real info on what settings have been used from day one, the base info is that the server chipset. let alone the normal one, allows both CPU and RAM overclocking and there is nobody saying that they didn't overclock either one of them.
I mean does anybody even know what the max official ram speed is for 4 modules on a 14900k? I couldn't find any info on that so I can't know if the server parts even had overclocked ram or not.
 
Did everybody miss the part where it says "engineering sample"?

Debating the numbers is a waste of time, there is no way of knowing if the final product will be like the sample.
 
thestryker said:
Says right on the chart what the supported speeds for the configurations of 1DPC (1 DIMM per channel) and 2DPC (2 DIMMs per channel) are. So that's your 2 and 4 DIMM configurations.
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Yeah so he is talking about putting 4 ddr5 dims to 4200 for the most stability which is above specs, 4 dimms, single rank even, max would be 4000.

And that is to make them stable after the degradation...overclock them after the degradation to make them more stable, at least that's how I interpreted that.
 
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