News AMD's Upcoming Phoenix CPUs to Feature Hybrid Design: Document

[-Fran-]

It will also mean that the small cores won't really be that much smaller or use that much less power...

Correct, but t's irrelevant to what I said. As bit_user pointed out, AMD has a slight advantage in manufacturing thanks to TSMC and they're using it as you'd expect.

Intel could have chosen to thin out the P-core by just not adding AVX512 in the design, but it seems like they were banking on the hopes they'd make the asymmetric ISA work in time.

I don't think what I'm trying to say here is that hard to understand, is it?

Regards.

 

[TerryLaze]

Correct, but t's irrelevant to what I said. As bit_user pointed out, AMD has a slight advantage in manufacturing thanks to TSMC and they're using it as you'd expect.

Intel could have chosen to thin out the P-core by just not adding AVX512 in the design, but it seems like they were banking on the hopes they'd make the asymmetric ISA work in time.

I don't think what I'm trying to say here is that hard to understand, is it?

Regards.

Or maybe intel didn't bother with making a second mask for p-cores without avx because they have the fabs to produce the chips so the size difference doesn't matter,and twice doesn't matter on desktop, and maybe AMD didn't make a second mask for e-cores without avx because they don't want to spend the money.

I mean if we are guessing we can guess in every direction.

 

[bit_user]

It sounds like you're trying to say ...

I'd summarize my points as:

• Intel had a greater need or desire for their E-cores to be as small and energy-efficient as possible (without being too slow).
• Intel introduced their (mainstream) hybrid CPU on a less dense process, meaning AVX-512 would've come at a greater cost.

These are the reasons why I think they arrived at different answers. If you change both (or maybe even just one) of those variables, then it's quite likely Intel would've put AVX-512 in Gracemont. Otherwise, AMD's present situation isn't really comparable to where Intel was at.

 

[bit_user]

Ok I have no idea if these are individual modules all under one name or if they are the same module doing different stuff, in either case it's a crapton of different things.
At some point they also added storeMI.
https://www.amd.com/en/press-releases/amd-takes-computing-2016dec13

​

AMD SenseMI technology is a key enabler of AMD's landmark increase of greater than 40 percent in instructions per clock1, and is comprised of five components:​

• Pure Power – more than 100 embedded sensors with accuracy to the millivolt, milliwatt, and single degree level of temperature enable optimal voltage, clock frequency, and operating mode with minimal energy consumption;
• Precision Boost – smart logic that monitors integrated sensors and optimizes clock speeds, in increments as small as 25MHz, at up to a thousand times a second;
• Extended Frequency Range (XFR) – when the system senses added cooling capability, XFR raises the Precision Boost frequency to enhance performance;
• Neural Net Prediction – an artificial intelligence neural network that learns to predict what future pathway an application will take based on past runs;
• Smart Prefetch – sophisticated learning algorithms that track software behavior to anticipate the needs of an application and prepare the data in advance.

Ah, thanks for digging that up!

Like branch prediction, Precision Boost and Smart Prefect are heuristic-based. Therefore, some form of machine learning might be applicable. However, you can bet it's either a very simple pre-baked neural network or some very basic form of "online learning".

BTW, what I seem to recall reading about Intel's Thread Director is that it uses a pre-trained neural network to classify threads into 4 categories, on the basis of various performance metrics it collects. However, I'm not sure if that neural network part is implemented in hardware or software.

 

[TerryLaze]

BTW, what I seem to recall reading about Intel's Thread Director is that it uses a pre-trained neural network to classify threads into 4 categories, on the basis of various performance metrics it collects. However, I'm not sure if that neural network part is implemented in hardware or software.

The point is they don't need MS to do anything new on windows as long as they can send similar tips to the MS part of the TD in windows.