"Lets assume you like me owned a business. Most of our business is about keeping the ear to the ground and making conjecture of the sources you have, because, big money giants like Intel can't afford the bad press. Its like , we pay 100x the R&D that our little competitor pays... they were on their knees 4 years ago and now they are stomping all over us... Lies and deception is the new perception."
Well, As I own 3 businesses and employ over 1000 people - and the spurious claim of owning a business - while the rest is just kinda /yawn
"TSMC is nothing to do with Intel. In fact let me enlighten you on ASICs and PCB manufacturing and design I teach at College level Lol."
Impressive, "own" a business and a teacher... I have designed and had manufactured quite a few PCBs for my home automation system... and didn't need to take a class for that.
"TSMC use a more traditional flat level approach to their Transistors. It was a wise and stable move. It did mean that the TSMC 7nm would be equivalent to Intels 10nm approach because hey ho, Intel not only wanted to go Finfet, but Phallic FinFET with their 3D stack of transistors where they would build them upwards. So in the same Lateral space, Intel can fit 3 Transistors where TSMC can only fit two...."
/yawn - and TSMC really knocked their long fragile supply chain out of the park. Phallic FinFET - that's a new one. Do you see phalluses in everyday scenes? Might need some professional help for that.
"Let me just give you a hint of something that you just don't get... The 3D FinFET design was Novel and inventive, but came with servere drawbacks and this is where Intel is in Deep Do do and this is why I know they are having yield problems and are now very eager to get to the 7nm conventional design and pretend their Novel idea never existed. So let me put my analystic type thoughts through to you... Intel has been stuck at the 10 nm node for .... HOW long? ... and still are not putting all its fabrication plants in the basket (which traditionally it does!) and has been criticized for being stuck in the dark ages of 14nm. So how does it mask the problems. It is pretending to be 14nm chipsets in 14nm and processors in 10nm yet the Graphics side of the chips are still 14nm. what does that tell you ...."
TL;DR
"Let me just give you a hint of something that you just don't get... The 3D FinFET design was Novel and inventive, but came with servere drawbacks and this is where Intel is in Deep Do do and this is why I know they are having yield problems and are now very eager to get to the 7nm conventional design and pretend their Novel idea never existed. So let me put my analystic type thoughts through to you... Intel has been stuck at the 10 nm node for .... HOW long? ... and still are not putting all its fabrication plants in the basket (which traditionally it does!) and has been criticized for being stuck in the dark ages of 14nm. So how does it mask the problems. It is pretending to be 14nm chipsets in 14nm and processors in 10nm yet the Graphics side of the chips are still 14nm. what does that tell you ...."
We still have not determined that Intel is having yield problems, your wall of text proved nothing. Analystic.. that's a new word - you make it up?
"Just check under the Lithographic progress chart for companies and progress and somehow Intel seems to be on the working and developed Fabrication of 7nm and 5nm already... So either that is true, and they are fabricating chips to put in your arm with the vaccine, or they are lying and struggling with the 10nm process under high risk of failures."
Intel has several processes in progress at any one time - 10nm "vanilla" is in HVM of MILLIONS of Ice Lake SP (yes Sapphire Rapids coming later this year, but the customer base for Ice Lake SP (VM farm mostly) is not the same as Sapphire Rapids). Their 10nm SF (big advance there is Cobalt which is needed at nano scale since copper becomes a resistor) is mostly the market dominating Tiger Lake and likely Nvidia's worst nightmare a 4 tile Xe HP compute GPU... And risk production started for 10nm ESF - as both that process and Intel's Full EUV 7nm are featured in the Xe HPC which is undergoing testing. Last I checked TSMC was not doing Cobalt and still only doing a couple of layers of EUV...
and the Anti Vax - WOW, just WOW. You Made my List - had I read that first, I would not have bothered to dignify your rambling circular logic with a response.
Good Luck in All Your Future Stupid Ventures - and those squiggly red lines under some words mean they are misspelled
My goodness, you are so full of yourself. Ok lets just pic apart your argument.
You says that you can Print PCBs at home... Wow, I'm impressed. This can easily be done with alkaline sets that I used to use 20 odd years ago. A messy mechanism and method, but yes, even a fool can make their own PCB's and generally only using thru'hole tech and usually employing 90 degree angles on their PCB on the traces that have problems with signal bouncing problems with high frequency signaling. The art of making complex PCBs is making them multilayer by stacking multiple micro thin slices of glass on top of each other, ultra thin lines and routing (with Via) that are way to small for your eyes to see. So if you are referring to the automated drilling systems that use simple coordinated Gerber files (which I use with my students programmed through PROTEUS), then how do you expect me to be impressed. You certainly have not produced a PCB with a reliable Soldermask or silkscreen, so I remain unimpressed.
Simply claiming they can make a PCB, because making an Ugly PCB is not hard at all and even my kids when they were young did it. So unless you are talking access to the complete process and not just the hand drawn stuff or the drilling cutter.
About spelling, I can be bothered to answer with much time or even correcting any mistakes on people like you, who don't have much knowledge on materials or ASICs. And when proper design terminology is SMT or "THRU'Hole" Tech (leet speak is considered good for an Engineering term) is used to describe componentry and tech on a board, I also don't give too much heed to spell checkers. In the engineering game, acronyms and terminology that is used is often flagged as red underlines, so I often ignore it when writing PCB design and manufacturer docs or comments. But obviously you are picking at straws.
And well done for reading about the Cobalt issue, but you clearly don't understand it. Copper still has a lower resistance than Cobalt, with the only exception of when the Copper etching and lining is poor allowing a diffusion of the copper into other materials (often tantalum) and thus spreading an impurity through the copper raising its resistance. And this is a problem when the fabrication process is not great and often causes yield problems (my point) when the lithographic lasers cause this process to happen. Intel classically uses the lie of calibration of the lasers can take months, but in their case Years.
My Assumption of the point of lower yields is based on Intel having a great track record of lying about all their failures in the past, and being as I am quite up on the knowledge of the RARE earth materials, being a proponent of trying to get them to use Carbon as a replacement, but they wont, because it means the Laser tech would have to change as Carbon is better than near all other materials for thermals, conduction and Quantum reactions, but as a result is also resistant to the laser and requires a complete change to how the fabrication is to be layered and set. It is also Immune to diffusion, if it is shaped correctly. But this would require years of revamping the tech (which they will eventually have to do) as the apparent size of an atom is 0.1nm for its current materials. Cobalt is a material that is similar to Graphene (carbon) in its properties, but still not as good over all. And yes you are wrong, Copper in its pure form has less resistance than Cobalt... Its just that Intel's design with its 10nm needs it because their copper always diffuses when trying to connect it to its Erected (hence the joke phallus) 3D Fin FETS that have 3 gates per lateral until space of TSMCs 2 gates... Yet because of the connection problems with the lateral transistor setup, they need a stronger material (cobalt to connect it and IMPROVE YIELDS.., DUH!
# 3 Businesses wow. I used to own just one before I got Cancer (probably due to not being careful around leaded solder for long periods. So now I am teaching because I can't do much more and won't even be employed by companies interested in my skill set. I was working in Dubai when I got sick, but even then I was training students, because I had enough of my ultra heavy schedule... My Business was small scale, so I am impressed if you are telling the truth... But I am guessing you are not.
Finally, as I said before many times, Intel rarely tells the truth, and even with my dealings with them, their techs were lying and twisting facts. When they were litigated constantly by AMD and other companies for stealing tech and unfair practices, I decided to hole up with AMD for products (despite their lack luster products). Now I am too old to care much, I don't even play games, but one of my Interests will always be PCB manufacture and design, especially as we near the Atomic limit. But How am I to produce evidence from the Great silicone Liars. So I have to go by my experience and how companies, like theirs lie to save face... And Intel likes to lie at the science level too... and few dare to question them.... Unless they can litigate.
If you trust to wait for Intel to tell the truth, then you'll be waiting for the Flat earthers to prove their point, because they are likely to happen at the same time. LOL
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