News Arm unveils next-gen Neoverse CPU cores and compute subsystems — hoping to entice more custom silicon customers

[Admin]

Arm reveals Neoverse V3, Neoverse N3, Neoverse E3 CPU cores, and compute subsystems.

Arm unveils next-gen Neoverse CPU cores and compute subsystems — hoping to entice more custom silicon customers : Read more

 

[bit_user]

I found these details of ARMv9.1-A:

• General Matrix Multiply (GEMM) instructions
• Fine grained traps for virtualization
• High precision Generic Timer
• Data Gathering Hint

...and ARMvv9.2-A:

• Enhanced support for PCIe hot plug
• Atomic 64-byte load and stores to accelerators
• Wait For Instruction (WFI) and Wait For Event (WFE) with timeout
• Branch-Record recording

Source: https://developer.arm.com/documentation/102378/0201/Armv8-x-and-Armv9-x-extensions-and-features

 

[DaveLTX]

V2 competes against Zen 4? I've only seen Graviton4 using V2 which is hardly a fleshed out roster of comparisons because I've hardly seen any comparison of AWS instances of Genoa Vs G4 either

 

[bit_user]

V2 competes against Zen 4? I've only seen Graviton4 using V2 which is hardly a fleshed out roster of comparisons because I've hardly seen any comparison of AWS instances of Genoa Vs G4 either

Nvidia's Grace uses Neoverse V2 cores. Overall, Genoa does better, even when you account for the difference in core count, but Grace does manage to chalk up a few notable wins.

Grace vs. 64-core and 96-core ThreadRipper:

https://www.phoronix.com/review/nvidia-gh200-amd-threadripper
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I would disregard the OpenVINO benchmarks, which probably just haven't been optimized for SVE2. Besides, if you're running Nvidia Grace, then you probably paired it with a Hopper GPU that's way faster at AI.

Here, it's compared against a bunch of Intel and AMD servers, in both 1P and 2P configurations:

https://www.phoronix.com/review/nvidia-gh200-gptshop-benchmark
​

Its Geomean is 95.2% of a 64-core Zen 4 EPYC 9554. Again, I think that's pretty good if you consider how lopsided a few of the benchmarks are towards x86 - they surely must be dragging down its score.

 

[jp7189]

Regarding memory support, the N3 portion of the article states the N3 support quad 40 bit channels. First, I thought ecc was 36 bits (32+4 for ecc) per channel. Second, this is essentially the same bandwidth as 128bit "dual channel" consumer desktops. That can't be right.

 

[bit_user]

Regarding memory support, the N3 portion of the article states the N3 support quad 40 bit channels. First, I thought ecc was 36 bits (32+4 for ecc) per channel.

No, it's correct. DDR5 has 8 bits of ECC per 32-bit subchannel. You're thinking of DDR4, which has 8 bits of ECC per 64-bit channel.

Second, this is essentially the same bandwidth as 128bit "dual channel" consumer desktops. That can't be right.

The comparison is apt. It's a 32-core, 32-thread SoC that you're comparing against a 16-24 core, 32-thread CPU. It's for smaller-scale edge servers and line cards.

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Note where it's scalable down to 8 cores and how it can run on only 40 W even for 32 cores! Running on such a modest power budget, and not their widest cores, you probably don't need more than about 128-bits worth of DDR5 bandwidth.

 

[jp7189]

No, it's correct. DDR5 has 8 bits of ECC per 32-bit subchannel. You're thinking of DDR4, which has 8 bits of ECC per 64-bit channel.

Thanks for that. I was shopping for ECC and found some Kingston ram that only supported 4 bits per channel (EC4). I generalized that to be the configuration of all DDR5 ECC. After reading your comment I dug deeper and now see there is an 8 bit mode (EC8) that I didn't notice before. It seems it's up to the memory controller and dram maker to choose either 4 or 8 in this generation. It's something I need to pay closer attention to when choosing components.