'bout RAM-s 'n L2 caches 'n mobo-s

[Guest]

Archived from groups: alt.comp.periphs.mainboard.fic (More info?)

I find it very important to clear out some oversights (or downsights) about
max instalable memmory in general. Is there, and where is it that one can
find the info 'bout this matter in general (for instance if one wants to
feed some old Pentium II board with RAM or alike). Witch part of a PC, MBo
or the CPU architecture declares this values of max insttalable RAM.
I 'm a proud ovner of VA503+ with 1 MB L2 cache on board, also have
2x128 pc 133 RAM instaled, with K6 II @ 500MHz. So what's my RAM upgrade
option. I'm looking for puttin' in it some more RAM. And witch BIOS settings
aply to it.


Thanx in advance!!

 

[Guest]

Archived from groups: alt.comp.periphs.mainboard.fic (More info?)

Mister Zorrila answerd this in downstanding thread in a post with
subject Re: Ram for VA-503+ to Steve.

But, the question remains concerning cachable RAM by means of L1 and L2
caches.
I understand in general L caches purpose, but I'm not certain on whitch
factor depends L caches capability of caching RAM.
Now, my question requires an explanation whitch includes understanding
the aproach how the operating systems handle running aplications
instructions codes.
It just may be that I'm starting to overcome the subject of this group.
But I see this questions and answers too often, and still can not conclude
why should L2 be a limit. There was a huge benchmark on Tom's Hware pages
and there you can see a page on adress:
http://www6.tomshardware.com/cpu/20030217/cpu_charts-06.html
whitch shows a PI 233 with 512 MB instaled.
So what's going on?

 

[Guest]

Archived from groups: alt.comp.periphs.mainboard.fic (More info?)

The circuits that provide L2 cache capability have limitations, and
the MVP3 chipset is only able to cache 256 Meg of memory due to the
size of the "tag ram", which is the device wherein the chipset keeps
track of cached memory pages. To put it simply, the tag ram
configuration determines how large an address space the caching
controller can keep track of, and accordingly, which pages of memory
are currently "in the cache". The MVP3 chipset boards make use of an
8-bit tag ram. In fact, there is a slight flaw in the implementation
of the MVP3 chipset and it's onboard tag ram, has something to do with
the "dirty bit", anyway the actual cached memory range is 255 Meg in
write-thru mode with 1 meg of L2 cache, and 127.5 Meg with write-back
cache mode.

I think the link below may help you understand L2 cache concepts and
caching restrictions.

http://www.stud.fernuni-hagen.de/q3998142/pcchips/howto/cache.html

For more information, use this google search string: "tag ram" mvp3
chipset
--
Best regards,
Kyle
"edi" <krarti@net4u.hr> wrote in message
news:c8u6nn$9qb$1@brown.net4u.hr...
| Mister Zorrila answerd this in downstanding thread in a post
with
| subject Re: Ram for VA-503+ to Steve.
|
| But, the question remains concerning cachable RAM by means of L1
and L2
| caches.
| I understand in general L caches purpose, but I'm not certain on
whitch
| factor depends L caches capability of caching RAM.
| Now, my question requires an explanation whitch includes
understanding
| the aproach how the operating systems handle running aplications
| instructions codes.
| It just may be that I'm starting to overcome the subject of this
group.
| But I see this questions and answers too often, and still can not
conclude
| why should L2 be a limit. There was a huge benchmark on Tom's Hware
pages
| and there you can see a page on adress:
| http://www6.tomshardware.com/cpu/20030217/cpu_charts-06.html
| whitch shows a PI 233 with 512 MB instaled.
| So what's going on?
|
|