If the cache line size for x64 is 64 bytes does that imply that every access to main memory results in 64 bytes being read, even for say a "mov ax, 0xFFFF"?
If a minimum of 64 bytes are always being read, would that be perfect for a dual channel memory layout (because then two burst reads from both channels would get you the 64 bytes)?
How wide is the bus for the uncore/infinity fabric for intel and AMD systems? Does the width of the IF or uncore bus vary if you have more memory channels (say a tri channel or quad channel memory controller as opposed to a dual channel memory controller)?
If a minimum of 64 bytes are always being read, would that be perfect for a dual channel memory layout (because then two burst reads from both channels would get you the 64 bytes)?
How wide is the bus for the uncore/infinity fabric for intel and AMD systems? Does the width of the IF or uncore bus vary if you have more memory channels (say a tri channel or quad channel memory controller as opposed to a dual channel memory controller)?
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