can a single lane of pcie do asynchronous read/write?

[i9-9999k]

https://en.wikipedia.org/wiki/PCI_Express

on the pcie wikipedia page it says "Per lane, in each direction: v2.x: 500 MB/s (5 GT/s)"

that kind of implies an aggregated throughput of 1 GB/s per lane (async read/write)

but i'm under the impression that a single pcie lane can only do a single direction at a given time (synchronous read/write)

https://en.wikipedia.org/wiki/I/O_Controller_Hub#ICH6

on this wikipedia page it says "ICH6 was Intel's first PCI Express southbridge. It made four PCI Express ×1 ports available. (in reality a PCI Express ×4 link with 1 GB/s per direction)"

that further proves what i believe is correct - that you need at least a x2 link to have asynchronous read/write

can someone spread some knowledge with me

 

[WyomingKnott]

The wikipedia article uses the term full-duplex, which means that the communication can run both ways at the same time. Hardwaresecrets, hardly a definitive source, states here that each lane is full duplex: http://www.hardwaresecrets.com/printpage/everything-you-need-to-know-about-the-pci-express/190

It's a full-duplex setup, with device-to-host and host-to-device on separate sets of wires in a lane and able to use both sets at the same time.

Not so much asynchronous, as simultaneous.

 

[i9-9999k]

The wikipedia article uses the term full-duplex, which means that the communication can run both ways at the same time. Hardwaresecrets, hardly a definitive source, states here that each lane is full duplex: http://www.hardwaresecrets.com/printpage/everything-you-need-to-know-about-the-pci-express/190

It's a full-duplex setup, with device-to-host and host-to-device on separate sets of wires in a lane and able to use both sets at the same time.

Not so much asynchronous, as simultaneous.

so that means i can send 500 MB/s each way simultaneously using a single pcie2 lane. totaling 1 GB/s aggregated throughput

i love hardwaresecrets, i'm surprised i hadn't seen that article yet. thanks for the link!

also, that means the wikipedia page for the intel ich6 is wrong, right? it should be a x4 link with 2 GB/s per direction?

edit: nope that wikipedia page isn't wrong because the intel ich6 uses pcie1 not pcie2. so each lane has 250 MB/s each way