gaurav71189 :
A correction needed:
"the remaining six HSIO serve the three USB 3.1 Gen2 ports"
There are only 2 USB 3.1 Gen2 ports (one type A and one type C at the back). Only one HSIO is used for the third USB 3.1 Gen1 port that is available as a header for type C. I believe the remaining 1 HSIO lane would be allocated to the GbE port. I'm not sure if the CNVi uses a lane.
Well what do you know, I must have temporarily mistaken it for an honest USB 3.1 Gen2 front-panel port rather than a sham version. As for the Ethernet, it's an i219V so it has an independent path and...oh crap, I checked the original table against the version you're seeing, they REMOVED i219V and replaced it with the word "Intel", as if that was useful. Thanks for asking a question I'd already answered, otherwise I wouldn't have looked for the error.
See if this makes more sense
😉
"The first PCIe x16 slot is fed by the CPU’s PCIe controller and doesn’t count toward the chipset’s 30-lane limit. The second x16-length slot has four chipset lanes, the four x1 slots have fixed pathways, and only one of the six SATA ports is a potential share (in the unlikely event that it gets lost to a SATA-based M.2 card). The upper and lower M.2 drive slots consume four and two lanes (respectively), the two rear-panel USB 3.0 ports takes up two more HSIO resources, the front-panel USB 3.0 header consumes only one HSIO through a USB hub, the USB 3.1 front-panel header consumes one HSIO since it's only connected to a Gen1 interface, and our math says that the four of the remaining six HSIO serve rear-panel USB 3.1 Gen2 ports. The two remaining HSIO pathways would seam to go to an unused M.2 Key-E interface, since the CNVi connector is cross-compatible with Key-E devices. All that said, for a budget-minded PC, the second (two-path) M.2 storage slot may likely go unused, rendering its lane count moot. "