Oh I wasn’t saying that pipeline length is the only thing that affects IPC, the parts feeding the pipeline are also important to IPC. And today’s AMD/Intel designs are actually dynamic pipeline length, I believe Zen and Intel can be 14-19 stages depending on workload. That’s actually not that much of an increase from the original Core architectures 12-stages and Core 2’s 16 stages. Mind you, Core came right after Netburst Prescott with its 31-stage pipeline. Sandybridge to kabylake Intel architectures have all maintained a 14-19 stage dynamic pipeline so not really that much longer than the original core. I can’t seem to find any data on the number of stages in alderlake and newer architectures however it seems both Intel and AMD have decided 14-19 stages is the optimal length.
I’m simply saying that shortening the pipeline is an easy way to increase IPC to compete with AMD/Intel if the 3a6000’s architecture is unable to hit similar IPC with the same pipeline length. And if they did decide to shorten the pipeline for said reason, then it could explain why 3 ghz with liquid nitrogen cooling is the max stable clock assuming SMIC’s 12nm process and loongson’s circuit design and layout is competently designed.
And then my addition of branch predictor design was just to show to add more reinforcement that it is much simpler to increase IPC by shortening the pipeline as longer pipelines require more and more sophisticated front end (branch prediction, instruction fetch, buffers, schedulers, etc.) and backend (catch population and hit rates, etc.) to maintain the same IPC as a shorter pipeline.
But you are right that front end and backend optimization is key to increasing IPC in long pipeline designs as the longer the pipeline, the more perfect the front/backend must be to keep the pipeline fully utilized. Like in my example with pentium 3/4, going from a 10-stage pipeline to a 20-stage pipeline required an increase of 566mhz clock speed to match the pentium 3’s performance despite pentium 4’s improved front/back end. And when Prescott came out, it’s 31-stage pipeline was so long that AMD had the better processor even though it couldn’t clock nearly as high.