Collection of AMD K10 data

[d4NjvRzf]

Anyone know what time zone is the reference for 9/10?

 

[spaztic7]

It is designed to compete with (and possibly beat, I'm not sure on that one...) the C2D/C2Q. I think Penryn is likely to beat K10.

Then for the sack of argument... what’s the point! Is AMD saying by not going to the high end that they give up? Are they admitting that they are second best? This is a sad, sad day if this is true.

Then again, it is AMD's own fault for waiting untill Intel caught up/ surpased them.

 

[shadowmaster625]

the only data that is relevant is that a barcy is only at most 15% faster than an X2 when processing a single thread or even a pair of threads. That means that a barcy 2350 (for $400) is no better than a $102 X2-4800 for all single and dual thread applications. That is unbelievable.... it means that AMD is essentially abandoning the desktop market.

 

[weskurtz81]

spaztic,

yeah, it's is pretty logical to assume that AMD can keep up with Intel when it comes to R & D with a very small amount of capital in comparison to what Intel is working with.

Shadowmaster625,

stop being a fanboy.

 

[PFZ1]

😴 So after all that crap DOES IT DO WHAT IT SAY ON THE BOX!!!! :lol:

 

[enewmen]

This is all great. But the K10 has been out for a while now. Where can I find a reliable performance per Mhz benchmark ?? Kentfield Vs. Phenom ?

 

[onestar]

Hmmmm, It appears to me that AMD is focusing on the server market.

That said, it might be time for me to upgrade my servers.

 

[cah027]

Here is a new Phenom video on youtube.

http://www.youtube.com/watch?v=q5-4u7NwGGw

 

[reconviperone1]

http://origin.arstechnica.com/staff/carthage.media/barcelona.gif

Barcelona ES:http://img259.imageshack.us/img259/4808/barcelonadieshotbygojdocf8.jpg

Barcelona die (11 metal layers, 283mm^2, 463M transistors):http://pc.watch.impress.co.jp/docs/2007/0214/kaigai_01l.gif

Barcelona waffer:http://img403.imageshack.us/img403/2628/barcelonawaferns2.jpg


Macro/micro-architectural improvements over K8:

Quad-core
- Native quad-core design
- Redesigned and improved crossbar(northbridge)
- Improved power management
- New level of cache added, L3 VICTIM
Power management - DICE(Dynamic Independent Core Engagement)
- PLLs for each core, clocked independently and varies clock speed depending on usage.
- ODMC power management: ability to shut down read channels if memory is only using writes and vice versa:
* Reduces the power consumption of the memory controller by up to 80% on "many" workloads.
- Aggressive grained clock gating
- Power management state invariant time stamp counter (TSC)
- Enhanced AMD's PowerNow - works independently without OS driver support
Virtualization improvements
- Nested Paging(NP):
* Guest and Host page tables both exist in memory.(The CPU walks both page tables)
* Nested walk can have up to 24 memory acesses! (Hardware caching accelerates the walk)
* "Wire-to-wire" translations are cached in TLBs
* NP eliminates Hypervisor cycles spent managing shadow pages(As much as 75% Hypervisor time)
- Reduced world-switch time by 25%:
* World-switch time: round-trup to Hypervisor and back
Dedicated L1 cache
- 256bit 128kB (64kB instruction/64kB data), 2-way associative
- 2 x 128bit loads/cycle
- lowest latency
Dedicated L2 cache
- 128bit 512kB, 16-way associative
- 128bit bus to northbridge
- reduced latency
- eliminates conflicts common in shared caches - better for virtualization
Shared L3 cache
- 128bit 2MB, 32-way associative
- Victim-cache architecture maximizes efficiency of cache hierarchy
- Fills from L3 leave likely shared lines in the L3
- Sharing-aware replacement policy
- Expandable
Independent DRAM controllers
- Concurrency
- More DRAM banks reduces page conflicts
- Longer burst length improves command efficiency
- Dual channel unbuffered 1066 support(applies to socket AM2+ and s1207+ QFX only)
- Channel Interleaving
Optimized DRAM paging
- Increase page hits
- Decrease page conflicts
Re-architect northbridge for higher bandwidth
- Increase buffer sizes
- Optimize schedulers
- Ready to support future DRAM technologies
Write bursting
- Minimize Rd/Wr Turnaround
DRAM prefetcher
- Track positive and negative, unit and non-unit strides
- Dedicated buffer for prefetched data
- Aggressively fill idle DRAM cycles
Core prefetchers
- DC Prefetcher fills directly to L1 Cache
- IC Prefetcher more flexible
* 2 outstanding requests to any address
HyperTransport 3
- Up to three 16bit cHT links
- Up to 5200MT/s per link
- Un-ganging mode: each 16bit HT link can be divided in two 8bit virutal links
- Can dynamically adjust frequency and bit width to save power
- AC mode (higher latency mode) to allow longer communications distances
- Hot pluggable

Barecelona pipeline (12/18 ALU/FPU stages): http://img162.imageshack.us/img162/6479/k8lexecutionpipelineye3.jpg

CPU Core IPC Enhancements:
Advanced branch prediction
- Dedicated 512-entry Indirect Predictor
- Double return stacksize
- More branch history bits and improved branch hashing
History-based pattern predictor
32B instruction fetch
- Benefits integer code too
- Reduced split-fetch instruction cases
Sideband Stack Optimizer
- Perform stack adjustments for PUSH/POP operations “on the side”
- Stack adjustments don’t occupy functional unit bandwidth
- Breaks serial dependence chains for consecutive PUSH/POPs
Out-of-order load execution
- New technology allows load instructions to bypass:
* Other loads
* Other stores which are known not to alias with the load
- Significantly mitigates L2 cache latency
TLB Optimisations
- Support for 1G pages
- 48bit physical address (256TB)
- Larger TLBs key for:
* Virtualized workloads
* Large-footprint databases and
* transaction processing
- DTLB:
* Fully-associative 48-way TLB (4K, 2M, 1G)
* Backed by L2 TLBs: 512 x 4K, 128 x 2M
- ITLB:
* 16 x 2M entries
Data-dependent divide latency
Additional fastpath instructions
– CALL and RET-Imm instructions
– Data movement between FP & INT
Bit Manipulation extensions
- LZCNT/POPCNT
SSE extensions
- EXTRQ/INSERTQ (SSE4A)
- MOVNTSD/MOVNTSS (SSE4A)
- MWAIT/MONITOR (SSE3)
Comprehensive Upgrades for SSE
- Dual 128-bit SSE dataflow
- Up to 4 dual precision FP OPS/cycle
- Dual 128-bit loads per cycle
- New vector code, SSE128
- Can perform SSE MOVs in the FP “store” pipe
- Execute two generic SSE ops + SSE MOV each cycle (+ two 128-bit SSE loads)
- FP Scheduler can hold 36 Dedicated x 128-bit ops
- SSE Unaligned Load-Execute mode:
* Remove alignment requirements for SSE ld-op instructions
* Eliminate awkward pairs of separate load and compute instructions
* To improve instruction packing and decoding efficiency

Most of the informations are from Ben Sander's presentation at AMD FPF 2006, but also there are other informations included from various internet sites.

AMD Software Optimization Guide for K10

Educative articles about K8L(K10):
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2939&p=1
http://www.xbitlabs.com/articles/cpu/display/amd-k8l.html
http://www.extremetech.com/article2/0,1697,2027644,00.asp
http://www.eetimes.com/news/semi/sh...K4CYB2QSNDLRSKHSCJUNN2JVN?articleID=193200399
http://www.channelinsider.com/article/AMD+Unveils+Barcelona+QuadCore+Details/191008_1.aspx
http://www.realworldtech.com/page.cfm?ArticleID=RWT060206035626
http://www.theregister.co.uk/2007/02/11/amd_enhanced_powernow/
http://www.tgdaily.com/2007/02/11/amd_barcelona/

AMD official statements and public presentations:
Syndrome-oc interview with Giuseppe Amato & Philip G. Eisler
HEXUS interview with Patrick Patla, Director of AMD Server Workstation Divisionhttp://www.hexus.tv/show.php?show=28
Interview with Randy Allen, AMD's corporate vice president for servers and workstations
AMD Developer Day, London Dec/06/2006 presentation
Game Developers Conference 2007, Justin Boggs AMD

Roadmap(speculative):

Server:
Opteron 8272SE 2.6GHz 120W TDP, socket F, 3 cHT links, 3600MT/s, DDR2-667, Q2 2008
Opteron 8270SE 2.5GHz 95W TDP, socket F, 3 cHT links, 3400MT/s, DDR2-667, Q3 2007
Opteron 8268SE 2.4GHz 89W TDP, socket F, 3 cHT links, 3400MT/s, DDR2-667, Q3 2007
Opteron 8266 2.3GHz 89W TDP, socket F, 3 cHT links, 3200MT/s, DDR2-667, Q3 2007
Opteron 8264 2.2GHz 89W TDP, socket F, 3 cHT links, 3200MT/s, DDR2-667, Q3 2007
Opteron 8262 2.1GHz 89W TDP, socket F, 3 cHT links, 3000MT/s, DDR2-667, Q3 2007
Opteron 8260HE 2.0GHz 68W TDP, socket F, 3 cHT links, 3000MT/s, DDR2-667, Q4 2007
Opteron 8258HE 1.9GHz 68W TDP, socket F, 3 cHT links, 2800MT/s, DDR2-667, Q4 2007
Opteron 2272SE 2.6GHz 120W TDP, socket F, 2 cHT links, 3600MT/s, DDR2-667, Q2 2008
Opteron 2270SE 2.5GHz 95W TDP, socket F, 2 cHT links, 3400MT/s, DDR2-667, Q3 2007
Opteron 2268SE 2.4GHz 89W TDP, socket F, 2 cHT links, 3400MT/s, DDR2-667, Q3 2007
Opteron 2266 2.3GHz 89W TDP, socket F, 2 cHT links, 3200MT/s, DDR2-667, Q3 2007
Opteron 2264 2.2GHz 89W TDP, socket F, 2 cHT links, 3200MT/s, DDR2-667, Q3 2007
Opteron 2262 2.1GHz 89W TDP, socket F, 2 cHT links, 3000MT/s, DDR2-667, Q3 2007
Opteron 2260HE 2.0GHz 68W TDP, socket F, 2 cHT links, 3000MT/s, DDR2-667, Q4 2007
Opteron 2258HE 1.9GHz 68W TDP, socket F, 2 cHT links, 2800MT/s, DDR2-667, Q4 2007
Opteron 1370SE 2.5GHz 95W TDP, socket AM2+, 1 cHT link, 3400MT/s, DDR2-1067, 2008
Opteron 1368SE 2.4GHz 89W TDP, socket AM2+, 1 cHT link, 3400MT/s, DDR2-1067, 2008
Opteron 1366 2.3GHz 89W TDP, socket AM2+, 1 cHT link, 3200MT/s, DDR2-1067, 2008
Opteron 1364 2.2GHz 89W TDP, socket AM2+, 1 cHT link, 3200MT/s, DDR2-1067, 2008
Opteron 1362 2.1GHz 89W TDP, socket AM2+, 1 cHT link, 3000MT/s, DDR2-1067, 2008

Desktop:
AgenaFX 2.6GHz, unknown TDP, socket 1207+(Quad FX), 2 cHT links, 3600MT/s. DDR2-1067, Q3 2007
AgenaFX 2.4GHz, unknown TDP, socket 1207+(Quad FX), 2 cHT links, 3600MT/s. DDR2-1067, Q3 2007
AgenaFX 2.4GHz, unknown TDP, socket 1207+(Quad FX), 2 cHT links, 3200MT/s. DDR2-1067, Q3 2007
AgenaFX 2.2GHz, unknown TDP, socket 1207+(Quad FX), 2 cHT links, 3200MT/s. DDR2-1067, Q3 2007
AgenaFX 2.4GHz, unknown TDP, socket AM2+, 2 cHT links, 3200MT/s. DDR2-1067, Q3 2007
AgenaFX 2.2GHz, unknown TDP, socket AM2+, 2 cHT links, 3200MT/s. DDR2-1067, Q3 2007
Agena 2.4GHz, 89W TDP, socket AM2+, 1 cHT link, 3600MT/s, DDR2-1067, Q4 2007
Agena 2.2GHz, 89W TDP, socket AM2+, 1 cHT link, 3200MT/s, DDR2-1067, Q4 2007
Kuma(dualcore) 2.8GHz, 89W TDP, socket AM2+, 1 cHT link, 4200MT/s, DDR2-1067, Q4 2007
Kuma(dualcore) 2.6GHz, 65W TDP, socket AM2+, 1 cHT link, 3800MT/s, DDR2-1067, Q4 2007
Kuma(dualcore) 2.4GHz, 65W TDP, socket AM2+, 1 cHT link, 3600MT/s, DDR2-1067, Q4 2007
Kuma(dualcore) LP 2.3GHz, 45W TDP, socket AM2+, 1 cHT link, 3400MT/s, DDR2-1067, Q1 2008
Kuma(dualcore) LP 2.1GHz, 45W TDP, socket AM2+, 1 cHT link, 3000MT/s, DDR2-1067, Q1 2008
Kuma(dualcore) LP 1.9GHz, 45W TDP, socket AM2+, 1 cHT link, 2800MT/s, DDR2-1067, Q1 2008


Roadmap sources:
http://www.dailytech.com/Final+AMD+Stars+Models+Unveiled+/article7157.htm?www.reghardware.co.uk
http://www.dailytech.com/More+Details+on+AMD+Stars+Chipsets/article7147.htm (2007-05-03)
http://www.cpilive.net/v3/inside.as...s/itnews.php?tid=746541&starttime=0&endtime=0 (2007-02-23)
http://trackingamd.blogspot.com/2007/02/barcelona-model-numbers-revealed.html
http://www.hkepc.com/bbs/itnews.php?tid=709944
http://www.dailytech.com/AMD+Quadcore+Opteron+Models+Unveiled/article5992.htm


P.S. Any additional data or informations will be highly appreciated

So the socket 1207+ fasn8 systems are still a go according to this chart, is that right?