Question DDR5 ECC RAM: 72 or 80 bit (I'm not asking about on-die but traditional fully fledged ECC) ?

[emcci]

I'm reading about ECC DDR5 RAM and I can't solve an issue I have. Putting this two DIMMs as an example:

1. https://www.kingston.com/datasheets/KSM48E40BD8KM-32HM.pdf
2. https://www.kingston.com/datasheets/KSM48R40BD8KMM-32HMR.pdf

Ignoring the fact that #2 it's registered, what I want to understand it's why #1 has x72 ECC but #2 has x80 ECC. I have been searching info on the internet that explains me why and I have been able to find very little...

From msi:

DDR5 modules add an extra 8-bits per 32-bit address for a total of 80-bits to handle error correction, compared to 72-bits on DDR4.

And from a reddit (🤷‍♂️) comment:

DDR5 is actually composed of two independent 32-bit sub-channels instead of one 64-bit channel. Each sub-channel needs its own parity chip, so you end up with (32+8)+(32+8) instead of (64+8) width -- and ten chips total.

If so, how DIMM #1 ECC works and how it differs from #2 one? I'm missing something here and I can't find what is it.

 

[hotaru.hino]

72-bit just means it's using EC4 instead of EC8. Micron has an example where you can see this.

 

[emcci]

Thanks for your answer! Yes, it seems like one it's using 4 ECC bits per channel and the other one 8.

72-bit just means it's using EC4 instead of EC8. Micron has an example where you can see this.

The point (maybe it wasn't clear enough in my question) what's the difference between having 4 ECC bits per channel instead of 8?

It's EC4 still SECDED (single error correction, double error detection)? What's the difference in data protection between EC4 and EC8?

 

[hotaru.hino]

Thanks for your answer! Yes, it seems like one it's using 4 ECC bits per channel and the other one 8.

The point (maybe it wasn't clear enough in my question) what's the difference between having 4 ECC bits per channel instead of 8?

It's EC4 still SECDED (single error correction, double error detection)? What's the difference in data protection between EC4 and EC8?

Found some info on https://lenovopress.lenovo.com/lp1021.pdf (bottom of page 2), but basically EC4 doesn't have SCDD support.

 

[emcci]

Well, I'm not an expert but I have tried to search about it and seems that SCDD it's for when a whole DRAM chip fails. It's really that?

Also a question that bothers me it's that the memory controller it's in the CPU die, so, it's taken for granted that CPUs that support ECC support both EC8 and EC4? Or you have to guess? I have been trying to find info about that for Intel Alder Lake family with 0 success...