Question DDR5 read/write CRC support in latest CPUs (AM5 and LGA 1700)

[tquark]

Do latest AMD Ryzen CPUs (Zen 4) support DDR5 read/write CRC feature? If I am not mistaken, Intel 13-generation CPUs do not support this:
"Alert: This signal is used at command training only. It is getting the Command and Address Parity error flag during training. CRC feature is not supported" (from https://edc.intel.com/content/www/u...-core-processors-datasheet-volume-1-of-2/002/).

Do AMD Ryzen (Zen 4) processors have advantages over Intel 13-gen processors (with Z690 or Z790 chipset) in terms of support for memory error detection and correction?

 

[kerberos_20]

ECC on ddr5 is for server mainboards only, they will not even fit into consumer mainboards, they are physicaly incompatible with DDR5 non ECC mainboards...and there arent even any server mainboards for 13th gen or ryzen 7000 cpu at all

soo look for mainboard which supports ECC, then slot in any compatible CPU (XEON/EPYC/Threadripper Pro) and there you go

 

[tquark]

ECC on ddr5 is for server mainboards only, they will not even fit into consumer mainboards, they are physicaly incompatible with DDR5 non ECC mainboards...and there arent even any server mainboards for 13th gen or ryzen 7000 cpu at all

It seems that ASUS Pro WS W680-ACE IPMI motherboard supports Intel 13th gen processors and DDR5 ECC RAM.

 

[tquark]

If I am not mistaken, Intel 13-generation CPUs do not support this:
"Alert: This signal is used at command training only. It is getting the Command and Address Parity error flag during training. CRC feature is not supported" (from https://edc.intel.com/content/www/u...-core-processors-datasheet-volume-1-of-2/002/).

In the Volume 2 of the datasheet I have found a register with field names containing "DDR5 CRC Error" (https://edc.intel.com/content/www/u...f-2/error-command-errcmd-0-0-0-pci-offset-ca/). Maybe read CRC is supported, write CRC is not supported. It seems that write CRC uses the Alert signal, but I don't know whether it is possible to implement write CRC without using the Alert signal.