Discussion: AMD Ryzen

[-Fran-]

True, but both the Marketing and Technical seem to be aligning in this particular case. AMD makes no mention of six-core parts in their release plans, and the design of the chip would indicate core counts will be in groups of four. With the technical and marketing in alignment, I don't understand why people are expecting something that almost certainly won't come to be.

Marketing and Technical teams aligned... Uhm... In AMD... Uhm...

I don't know, gamerk, that is a *VERY* hard sell, haha.

Cheers!

 

[cdrkf]

True, but both the Marketing and Technical seem to be aligning in this particular case. AMD makes no mention of six-core parts in their release plans, and the design of the chip would indicate core counts will be in groups of four. With the technical and marketing in alignment, I don't understand why people are expecting something that almost certainly won't come to be.

Marketing and Technical teams aligned... Uhm... In AMD... Uhm...

I don't know, gamerk, that is a *VERY* hard sell, haha.

Cheers!

Yeah I can't see anything that currently precludes a hex core part imo. The die will evidently be built as either a quad or octa-core part but surely defective 8 core dies can be salvaged without disabling half the chip?

I mean you agree it's possible to disable 1 core in a monolithic quad core? So why is it not possible to disable individual cores even if the cores are built into groups of 4? I don't understand why the physical layout of groups of 4 means they are somehow intrinsically tied together in such a way that you *must* disable the whole block. A 6 core part from an 8 core die is a much more efficient use than cutting it in half imo.

 

[ComputerSecurityGuy]

Especially considering a quad core out of eight core die would be a significant loss. The value would drop on the order of $300ish or more per chip, maybe as much as $500.

 

[juanrga]

My point was to say "marketing != technical" and also to remind you all that no one here *really knows* what can or can't be disabled without a hands on of the actual manufacturing and/or detailed design of the core.

The marketing dept. is irrelevant to the fact that the there is only 8-core and 4-core engineering samples. And don't forget that about two years ago I predicted Zen would come in clusters of four-cores each. The marketing dept didn't play any role in my prediction.

 

[ComputerSecurityGuy]

Yes, but would you have ES of semi-defective parts?

 

[juanrga]

Yeah I can't see anything that currently precludes a hex core part imo. The die will evidently be built as either a quad or octa-core part but surely defective 8 core dies can be salvaged without disabling half the chip?

I mean you agree it's possible to disable 1 core in a monolithic quad core? So why is it not possible to disable individual cores even if the cores are built into groups of 4? I don't understand why the physical layout of groups of 4 means they are somehow intrinsically tied together in such a way that you *must* disable the whole block. A 6 core part from an 8 core die is a much more efficient use than cutting it in half imo.

The reason is the same why Intel has a core granularity of two cores: balance. When one core is defective, Intel has to disable it and its partner even when the partner core is fully operational (from a silicon point of view).

 

[juanrga]

Yes, but would you have ES of semi-defective parts?

The 65W quad-core ES use the same die than the 95W octo-core ES, but with four cores disabled due to defects.

 

[-Fran-]

The marketing dept. is irrelevant to the fact that the there is only 8-core and 4-core engineering samples. And don't forget that about two years ago I predicted Zen would come in clusters of four-cores each. The marketing dept didn't play any role in my prediction.

Since you like facts... How does Intel sample ESes? Do they sample all the way down to the Pentium harvested dies or just Quad and Dual of a certain type?

What about -E versions of the dies?

I don't know how they do it, so I'm not implying I do know, by the way.

Cheers!

 

[cdrkf]

@Juan what I don't understand then is how the old x3 parts came into existence? I would understand having to disable 1 core in each cluster to make a hex core as opposed to two in one cluster, as that would result in an uneven amount of level 3 cache between the cores (although they could reduce the level 3 on the cut side to compensate?)...

I'm not saying a hex core is a given, it quite likely won't feature in the launch line up (as it would be a salvaged design rather than a specific sku like the dozer' hex core), however I still think they will show up at some point....

 

[turkey3_scratch]

This thread is too technical for me 😛 I'll just wait for benchmarks.

 

[juanrga]

@Juan what I don't understand then is how the old x3 parts came into existence? I would understand having to disable 1 core in each cluster to make a hex core as opposed to two in one cluster, as that would result in an uneven amount of level 3 cache between the cores (although they could reduce the level 3 on the cut side to compensate?)...

I'm not saying a hex core is a given, it quite likely won't feature in the launch line up (as it would be a salvaged design rather than a specific sku like the dozer' hex core), however I still think they will show up at some point....

Not all microarchitectures are equal. In some you can disable individual cores, in others you can disable only pair of cores, and in other you can only disable four-cores.

Disabling one core in each cluster would unbalance both cluster, with one of the cores not having its partner. It is the same reason why Intel cannot disable a single core: there is no 5-core, 7-core, 9-core Broadwell-E, for instance. When you disable one core you have to disable the opposite to balance the loads, the ring, and probably the power management is affected as well.

What is a fact is that the engineering samples are 4-core and 8-core; the official mobile and desktop roadmaps only show 4-core and 8-core, and the server roadmap shows the same trend. There is a 32-core server and then a 24-core server, but not 28-core server.

 

[ComputerSecurityGuy]

But would the 24 core server have three eight core dies? Somehow having three dies seems unbalanced as well. (I hope dies are the right word).

 

[turkey3_scratch]

This thread is too technical for me 😛 I'll just wait for benchmarks.

We won't get any benchmarks this year.

I never said we would. I wait for lots of stuff that is coming out in years. Like all the upcoming Star Wars movies past Rogue One.

 

[Melonious]

Hi guys, there have been some leaked benchmarks.

I have a question, though. Any word on the price now that arrival is imminent?

 

[ComputerSecurityGuy]

Well, IF performance is somewhere between Ivy Bridge and Broadwell (which it still looks to be, but we aren't sure) then pricing will PROBABLY be the $200-250 mark for the 4C/8T version and somewhere between $500-1000 for 8C/16T.

 

[gamerk316]

But would the 24 core server have three eight core dies? Somehow having three dies seems unbalanced as well. (I hope dies are the right word).

From a design perspective, each "module" is a fully independent unit. See: 6-core CPUs. [two modules times three]..

 

[-Fran-]

But would the 24 core server have three eight core dies? Somehow having three dies seems unbalanced as well. (I hope dies are the right word).

From a design perspective, each "module" is a fully independent unit. See: 6-core CPUs. [two modules times three]..

The same can be said about Intel's HT... Disabling the additional registers for the HT part should be hard to do right? Yet they have i3s, Pentiums (with disabled AVX functionality no less!) and i5 with i7s.

I've been looking the diagrams and I can find nothing that tells me they can't limit/split the CPU however they please. So, my conclusion is they don't need to do it *yet*. I'm sure in due time they will show more variants.

Cheers!

 

[cdrkf]

This looks interesting:
http://www.pcworld.com/article/3109327/hardware/let-the-cpu-wars-begin-amd-shows-its-zen-cpu-can-compete-with-intels-best.html

At same clock speed 8 core zen faster than 8 core Broadwell-E in blender...

 

[gamerk316]

In other news:

http://www.anandtech.com/show/10578/amd-zen-microarchitecture-dual-schedulers-micro-op-cache-memory-hierarchy-revealed

Details!

 

[TechyInAZ]

In other news:

http://www.anandtech.com/show/10578/amd-zen-microarchitecture-dual-schedulers-micro-op-cache-memory-hierarchy-revealed

Details!

Thanks! Added to list.

Zen is looking way better than I expected it to be.

 

[ComputerSecurityGuy]

I know! Looks like a slight but solid edge over Haswell. Which is quite good. And even if they cherry picked the benchmark, Blender is a good example of what people will do with eight cores.

And if AMD drops quad core Zen at the $200-250 price point it will slice a nice chunk out of the i7 market.

 

[juanrga]

This looks interesting:
http://www.pcworld.com/article/3109327/hardware/let-the-cpu-wars-begin-amd-shows-its-zen-cpu-can-compete-with-intels-best.html

At same clock speed 8 core zen faster than 8 core Broadwell-E in blender...

Blender is FP heavy benchmark.

@ 3GHz Broadwell 8C gives a maximum throughput of 768 GFLOPS.
@ 3GHz Zen 8C gives a maximum throughput of 384 GFLOPS.

Therefore it is evident that they are playing with compiler settings to get Zen achieve the same performance than Broadwell-E. Moreover, Blender code mix is unusual and must be favoring the four half FP pipes of Zen over the two full pipes on Broadwell microarchitecture.

Excellent marketing move!

 

[Melonious]

Well, IF performance is somewhere between Ivy Bridge and Broadwell (which it still looks to be, but we aren't sure) then pricing will PROBABLY be the $200-250 mark for the 4C/8T version and somewhere between $500-1000 for 8C/16T.

Thanks, buddy. In that case if they will likely have have some ~300 range seletions, I will probably wait for zen then.

I would hate to get more ddr3 ram anyway since it's probably on its last gasp and ddr4+ will be the norm soon.

 

[juanrga]

In other news:

http://www.anandtech.com/show/10578/amd-zen-microarchitecture-dual-schedulers-micro-op-cache-memory-hierarchy-revealed

Details!

Which confirms most (all?) of what I said. I like to see they confirming my prediction that Zen is 6-issue (as Sandy/Ivy, Haswell/Broadwell are 8-wide) and that the core has two schedulers: one for FP and other for integer/mem. Desdrenboy predicted three schedulers.

I also predicted 3GHz base clock and they have Zen silicon working at 3GHz. They claim are still confident to get higher clocks, but I don't expect anything above 200MHz.

This slide is interesting

It illustrates that I have been saying for months. 14LPP is a mobile-class process. It is optimized for efficiency and lower clocks. Once you go to the high-frequency regime the process start being more and more inefficient and if they had extrapolated the graph they would show the 14nm curve crossing the 28nm curve. At that crossing point 14nm will be poor than 28nm. I guess the crossing point will be somewhat around 4.5GHz where Zen will hit a power wall and will not overclock well. In fact I doubt that average Zen will hit 4.5GHz even with watter cooling.

 

[juanrga]

Worth also mentioning that AMD finally admits that Zen launches in 2017...