Mousemonkey :
Sakkura :
The AMD slide does say FinFET enables the drive to 16nm and beyond, so eh. These process node numbers are kinda fudged anyway.
I would love to see an explanation on the differences between the 14nm process and the 16nm process because from what I've found they appear to be the same and it is just a nomenclature thing that allows the process to be referred to as either 14nm or 16nm.
They're definitely different. GloFo is license-building on Samsung's 14nm FinFET process, while TSMC have their own 16nm FinFET process. In fact there are more processes available. TSMC had their first-gen 16nm FF, then 16nm FF+ and FFC. Nvidia is using 16FF+ for Pascal. Samsung has 14LPE and 14LPP, of which AMD, by way of GloFo, is using the latter.
There have been some eyes on this, especially when Apple dual-sourced their A9 SOC from TSMC and Samsung. I believe they used the same TSMC 16FF+ as Nvidia is using now, whereas they were using the 14LPE process from Samsung rather than the 14LPP process that AMD is basing Polaris on.
Here is an Anandtech article about the A9. While the comparisons there won't necessarily translate as 14LPE and 14LPP are not the same, at least you get an idea of what's going on.
In theory, you'd expect the same chip design to be 31% larger if built on a 16nm process than on a 14nm process. But it turns out the A9 is only 9% bigger on TSMC 16FF+ than on Samsung 14LPE. So the size difference between these examples of "16nm" and "14nm" is smaller than advertised. If you compare against Intel's 14nm process, that's also quite different in terms of density (see below). But then when you get into the details of it,
there are other important aspects than just the dimensions of the transistors.