Does AMD has some future?

[juanrga]

Well, algorithms scale poorly most of the time, so taking advantages of a full paradigm shift (bazillion cores) will take a lot of years.

In particular, I'm still curious as to how the ASM paradigm will be shifted for the bazillion core era. You feed the CPUs instructions in serial manner, right? Am I missing something there?

There are studies about how to run a serial workload over several cores to improve their performance. Even highly serial algorithms saw speed up of 8x running on 64 different cores in a manycore. But there are limits to this approach.

Algorithms with large amounts of parallelism are split into threads with each running on a different core.

If you feed the CPU with a thread, what the CPU does is to identify the hidden parallelism on the stream of instructions (the sequence of ASM) and then execute the instructions on parallel to speed up. The problem is that ordinary CPUs logic (superscalar/OOOE) spend too power and die area to identify the hidden parallelism in a sequential stream of instructions and don't scale up. Haswell can execute a maximum of eight instructions at once but sustained average is about 3 or 4 due to the logic being limited to a 192 ROB window. To achieve eight instructions sustained rate the ROB would be increased at 1000--2000 entries, but the area/power penalty is superlineal. and Haswell is already a big/complex core.

I can see that and undestand why, but you still feed the CPUs (no matter how many there are) in a serial fashion. I want to know if that is a design restriction of CPUs or OSes. That's why you can do parallel work on serial loads, because you get the "illusion" of parallelism. Strictly speaking, a serial algorithm can be made parallel in chunks, but the atomic operation that come out of that will still be feed sequentially to the CPU(s) in assembler/binary. I think I'm missing memory management a bit on my thinking... Ugh, I'll have to go back and read memory management again (pointers and registers).

Cheers!

No sure what are you really asking but I will try to answer.

Most commercial CPUs are based in the von Neumann paradigm, which is essentially a simple sequential paradigm where one thing is made at one time and as controlled by the program counter. Modern architectures (superscalar, VLIW) use 'tricks' to get hidden parallelism and speed up the serial stream, but that is all.

There are attempts to develop parallel paradigms, such as the dataflow model.

The dataflow computing model is known to overcome the limitations of the von Neuman paradigm by fully exploiting the parallelism inherent in programs. In the dataflow model, the operations are made when the data is available to the operands without any pre-determined order. Unlike the von-Neumann model, the dataflow model is neither based on memory structures that require inherent state transitions, nor does it depend on a program counter to sequentially execute a program.

However it has found difficulties for its practical implementation

http://en.wikipedia.org/wiki/Dataflow_architecture

 

[juanrga]

When Juan says 20% IPC gain i must ask in what instruction set? To see those level of gains is extraordinary if on average.

the near 20% gain is for x86 workloads

http://wccftech.com/intel-skylake-benchmarks-leaked-sisoftware-sandra/

For AVX kind of workloads the max. IPC gain is 2x because Skylake brings new 512bit SIMD units (Haswell uses 256bit units).

SiS have been never a good source of information about performance. Their benchmarks are just synthetics and no information about base/turbo clocks etc.

Also I'm reading also leaks about Intel's CPUs and Skylake seem to be design full of cool, new features and IPC similar to Haswell/Broadwell. AVX512 is one of these feature, not interesting for gamers.

SiS results agree with my early expectations: 5--10% per gen.

AVX512 must not be of direct interest to gamers (still) but there is life beyond games.

 

[juanrga]

This thread was started as a temporary thread would die soon once the main was fixed. But nobody is doing it, I see.

The title is not adequate to make this thread a substitute of the other.

I think that a new thread with the title "AMD's Future Chips: News, Rumors & Reviews" could be launched and all us move to it. jdwii suggests some mod to rename this. Ideas? Agree/disagree?

 

[juanrga]

However, improved branch prediction logic could easily squeeze more out of the available cache we have now. In fact, if AMD could improve that quite a bit, that would be some proverbial "low hanging fruit" in terms of the fact that they already will have the space dedicated to cache on the die anyway. In terms of actual execution, well they would have to come up with a better way to decrease missed predictions and increase efficiency in the pipelines. FAR easier said than done...however, in terms of improving CPU performance within the same or smaller footprint, branch prediction is a big area where you can make up a lot of ground, and increase power efficiency with the same stroke.

Precisely the way that AMD is going to reduce the branch misprediction penalty is not by improving the predictor accuracy but by reducing the pipeline depth, which has the side-effect of reducing considerably the maximum clocks achievable. That is why Opteron, FX based excavators are not coming and why any APu above 35W vanished in the air.

Rumor is that Excavator core tops at about 3GHz and that Carrizo CPU will be a step backward from Kaveri CPU. We will see.

What is funny is how AMD pursued a speed-demon CMT approach with Bulldozer and in each new iteration they are moving away. Steamroller was a step away from CMT with the double decoder, and now Excavator is a step away from speed-demon.

 

[szatkus]

Haha @ HL3 confirmed...

Actually...rumor is it may be here sooner than later...

I was just kidding. HL was great, but i've never liked HL2. But I'm waiting for Portal 3... somewhere in next 20 years....

 

[szatkus]

When Juan says 20% IPC gain i must ask in what instruction set? To see those level of gains is extraordinary if on average.

the near 20% gain is for x86 workloads

http://wccftech.com/intel-skylake-benchmarks-leaked-sisoftware-sandra/

For AVX kind of workloads the max. IPC gain is 2x because Skylake brings new 512bit SIMD units (Haswell uses 256bit units).

SiS have been never a good source of information about performance. Their benchmarks are just synthetics and no information about base/turbo clocks etc.

Also I'm reading also leaks about Intel's CPUs and Skylake seem to be design full of cool, new features and IPC similar to Haswell/Broadwell. AVX512 is one of these feature, not interesting for gamers.

SiS results agree with my early expectations: 5--10% per gen.

SiS were far from actual performance many times. I won't treat it as good source.

[
AVX512 must not be of direct interest to gamers (still) but there is life beyond games.

Most of professional users also doesn't need AVX512. In first place they need software. Very few can develop, compile and use their own code.
Anyway it's nothing ciritical for AMD.

 

[szatkus]

This thread was started as a temporary thread would die soon once the main was fixed. But nobody is doing it, I see.

The title is not adequate to make this thread a substitute of the other.

I think that a new thread with the title "AMD's Future Chips: News, Rumors & Reviews" could be launched and all us move to it. jdwii suggests some mod to rename this. Ideas? Agree/disagree?

+1

 

[szatkus]

However, improved branch prediction logic could easily squeeze more out of the available cache we have now. In fact, if AMD could improve that quite a bit, that would be some proverbial "low hanging fruit" in terms of the fact that they already will have the space dedicated to cache on the die anyway. In terms of actual execution, well they would have to come up with a better way to decrease missed predictions and increase efficiency in the pipelines. FAR easier said than done...however, in terms of improving CPU performance within the same or smaller footprint, branch prediction is a big area where you can make up a lot of ground, and increase power efficiency with the same stroke.

Precisely the way that AMD is going to reduce the branch misprediction penalty is not by improving the predictor accuracy but by reducing the pipeline depth, which has the side-effect of reducing considerably the maximum clocks achievable. That is why Opteron, FX based excavators are not coming and why any APu above 35W vanished in the air.

Rumor is that Excavator core tops at about 3GHz and that Carrizo CPU will be a step backward from Kaveri CPU. We will see.

What is funny is how AMD pursued a speed-demon CMT approach with Bulldozer and in each new iteration they are moving away. Steamroller was a step away from CMT with the double decoder, and now Excavator is a step away from speed-demon.

... I'll reply to it tomorrow... You should read RWT more carefully...

 

[etk]

Since the process name isn't based on any measurement anymore, saying 14nm doesn't really mean much. The truth is that GF's (Or Samsung's, or TSMC...) 16nm process is not anywhere near as small as Intel's 14nm node. GF's 16nm, 20nm, and 28nm all share minimum feature size, the improvement is just supposed to reflect power improvements (Marketing has a say in picking node names anymore). Relying on FF to reduce leakage is great for low power devices at low frequencies, but it doesn't do as much at higher clock rates; AMD will continue to see Fmax thermally limited on their performance x86 cores. This is why AMD is focusing on low power and embedded, it plays to their strengths in design and away from their weaknesses in manufacturing. This allows them to survive as a company. Maybe if processes begin to plateau they'll be able to challenge Intel like back in the day, but that won't be for at least 5 years.

 

[jdwii]

^^^^ Actually the opposite i believe will be true, once Amd can't simply shrink their design and add more transistors they will have to come up with a better architecture itself something i can't see them being able to do(well i mean beat intel's design).

The more we continue to be stuck with a fabrication process and unable to further improve without great effort the more each transistor matters.

 

[ohiou_grad_2006]

I don't pretend to know everything about the inner workings of CPU's, but I will say I've been using AMD cpu's since the k6 days. I've heard for quite a while how AMD was doomed, and they seem to always pull a rabbit out of their hat. I think if they get performance in the same ballpark as Intel come next release, people will buy it. Having the graphics business and console business has really helped them I think.

 

[jdwii]

I don't pretend to know everything about the inner workings of CPU's, but I will say I've been using AMD cpu's since the k6 days. I've heard for quite a while how AMD was doomed, and they seem to always pull a rabbit out of their hat. I think if they get performance in the same ballpark as Intel come next release, people will buy it. Having the graphics business and console business has really helped them I think.

Appealing to tradition is what logical fallacy you are using i believe and its something one should avoid.

"X has always been done. Therefore X is right.

Claim something to be well-established and proven. Say that it is traditional, and that to change it would be sacrilegious or very wrong in some way."

Not only that but CPU's more specifically X86 has gotten way more complicated over the years. I personally think Amd will be fine but not in the way they are today i think they will turn into a SOC company juan does as well. If you look at their actions it would point to this as well.

 

[gamerk316]

If AMD survives, it will be competing against other ARM makers. Problem is, AMD still lacks an ARM core, X86 is basically dead in mobile, and Intel and NVIDIA are both putting significant effort in that space. Heck, even VIA is in a better place then AMD right now.

 

[juanrga]

When Juan says 20% IPC gain i must ask in what instruction set? To see those level of gains is extraordinary if on average.

the near 20% gain is for x86 workloads

http://wccftech.com/intel-skylake-benchmarks-leaked-sisoftware-sandra/

For AVX kind of workloads the max. IPC gain is 2x because Skylake brings new 512bit SIMD units (Haswell uses 256bit units).

SiS have been never a good source of information about performance. Their benchmarks are just synthetics and no information about base/turbo clocks etc.

Also I'm reading also leaks about Intel's CPUs and Skylake seem to be design full of cool, new features and IPC similar to Haswell/Broadwell. AVX512 is one of these feature, not interesting for gamers.

SiS results agree with my early expectations: 5--10% per gen.

SiS were far from actual performance many times. I won't treat it as good source.

[
AVX512 must not be of direct interest to gamers (still) but there is life beyond games.

Most of professional users also doesn't need AVX512. In first place they need software. Very few can develop, compile and use their own code.
Anyway it's nothing ciritical for AMD.

"Were far from" doesn't imply this is happening this time. And as said I am not accepting the benchmarks per se, but because the leaks agree with what I was expecting.

AVX-512 will push convergence between KNL Phi and Skylake Xeon. Intel is heavily investing in AVX-512 and companion ISAs because x86 is at its limits and the only way to significantly increase performance in the next years will be by using the new ISAs. AVX-512 will hurt AMD on HPC and servers, almost killing HSA even before starts.

Regarding general users I know developers that want adopt AVX-512 (and future AVX-1024) for games and other general workloads, but it is a chicken and egg problem.

 

[juanrga]

However, improved branch prediction logic could easily squeeze more out of the available cache we have now. In fact, if AMD could improve that quite a bit, that would be some proverbial "low hanging fruit" in terms of the fact that they already will have the space dedicated to cache on the die anyway. In terms of actual execution, well they would have to come up with a better way to decrease missed predictions and increase efficiency in the pipelines. FAR easier said than done...however, in terms of improving CPU performance within the same or smaller footprint, branch prediction is a big area where you can make up a lot of ground, and increase power efficiency with the same stroke.

Precisely the way that AMD is going to reduce the branch misprediction penalty is not by improving the predictor accuracy but by reducing the pipeline depth, which has the side-effect of reducing considerably the maximum clocks achievable. That is why Opteron, FX based excavators are not coming and why any APu above 35W vanished in the air.

Rumor is that Excavator core tops at about 3GHz and that Carrizo CPU will be a step backward from Kaveri CPU. We will see.

What is funny is how AMD pursued a speed-demon CMT approach with Bulldozer and in each new iteration they are moving away. Steamroller was a step away from CMT with the double decoder, and now Excavator is a step away from speed-demon.

... I'll reply to it tomorrow... You should read RWT more carefully...

I believe it was a "Linux Forum" :lol:

 

[juanrga]

Since the process name isn't based on any measurement anymore, saying 14nm doesn't really mean much. The truth is that GF's (Or Samsung's, or TSMC...) 16nm process is not anywhere near as small as Intel's 14nm node. GF's 16nm, 20nm, and 28nm all share minimum feature size, the improvement is just supposed to reflect power improvements (Marketing has a say in picking node names anymore). Relying on FF to reduce leakage is great for low power devices at low frequencies, but it doesn't do as much at higher clock rates; AMD will continue to see Fmax thermally limited on their performance x86 cores. This is why AMD is focusing on low power and embedded, it plays to their strengths in design and away from their weaknesses in manufacturing. This allows them to survive as a company. Maybe if processes begin to plateau they'll be able to challenge Intel like back in the day, but that won't be for at least 5 years.

Roughly:

GF/TSMC 28nm node --> 28nm
GF/TSMC 20nm node --> 20nm
TSMC 16nm node --> ~18nm
GF 14nm node --> ~18nm
Intel 14nm node --> ~16nm

AMD doesn't have resources to pay for the latest node, Thus albeit rest of foundries are caughting Intel, AMD will be relegated to older nodes. This is why AMD is remaining on the 28nm for a while whereas competence are moving to 20nm and FF.

Moreover, even if AMD had access to latest nodes, they don't have the resources for the microarchitectures. In the past AMD did spend on R&D about one-half of what Intel did. During last years Intle has increased the R&D budget, whereas AMD has reduced. Today AMD did spend on R&D about one-tenth of what Intel does. No, they will not challenge Intel anymore and in fact the company is manoeuvring towards markets where Intel is not interested just to avoid any competition.

 

[qubits]

http://www.hsafoundation.com/ totally over your head that amd doesnt go it alone.. in fact the new gpu's they are releasing are suppose to be 20nm and samsung may supply them with 14nm

 

[juanrga]

If AMD survives, it will be competing against other ARM makers. Problem is, AMD still lacks an ARM core, X86 is basically dead in mobile, and Intel and NVIDIA are both putting significant effort in that space. Heck, even VIA is in a better place then AMD right now.

Yes, AMD is very late to the ARM-party, and lacks the resources other companies have (hey! even Nvidia now spends more money on R&D than AMD). But I think the main problem is the evident lack of any serious plan for the future.

For instance, some time ago AMD mentioned aggressive ARM server plans, but it was all waporware. The 16-core Seattle was canceled in few months, the 8-core was going to be released before the end of 2014, but never was. AMD did claim to have the server experience and the channels that other companies didn't. The reality is that newcommers like APM are already shipping ARM servers that are better than (Canceled? Delayed?) Seattle and others like Cavium have been selected by Cray for powering future ARM-based supercomputers.

AMD hit a new record here. Nobody did like their last x86 servers and now nobody want their ARM servers.

Nvidia is shipping Tegras with 32bit A15 and now with 64bit A57/A53 cores. The reason AMD cannot is because lacks a competitive graphics architecture as Maxwell.

AMD says us that their custom cores (K12 and Zen) won two design win for 2016. The problem is that they expect only 300 million per year in revenue. This is about one third of what Nvidia spends on R&D. Thus, I suspect that the cores are not so good and AMD is competing with aggressive pricing to get the designs.

 

[juanrga]

http://www.hsafoundation.com/ totally over your head that amd doesnt go it alone.. in fact the new gpu's they are releasing are suppose to be 20nm and samsung may supply them with 14nm

HSA is little more than a relabeling of former AMDs FSA (Fusion System Architecture). In any case, as explained before HSA is reinventing the wheel and doing it square.

The info that I have is that series 300 GPUs are build on 28nm not 20nm. And yes Samsung will supply them 14nm through Glofo. The question is when: 2016? 2017?

 

[qubits]

whats really so great about maxwell? when i look at the difference in the gtx 970 and the 780 the 970 really just gets a win with a higher clock and a extra gig of vram. everything else just falls on the efficiency side.
i know your not talking about gaming but that is what is important to me without much regard to power draw and honestly its going to take a benchmark to tell the difference in a 970 and a 290 especially when you go higher than 1080p so if anything it shows that maxwell has a lean memory bus and they should have stuck with 384bit.

 

[qubits]

i dont think there is anything about trying to fit a cube in a circle.. the whole technology industry is moving to gpu accelerated parallelism

 

[8350rocks]

http://www.hsafoundation.com/ totally over your head that amd doesnt go it alone.. in fact the new gpu's they are releasing are suppose to be 20nm and samsung may supply them with 14nm

HSA is little more than a relabeling of former AMDs FSA (Fusion System Architecture). In any case, as explained before HSA is reinventing the wheel and doing it square.

The info that I have is that series 300 GPUs are build on 28nm not 20nm. And yes Samsung will supply them 14nm through Glofo. The question is when: 2016? 2017?

Juan, AMD started HSA as an open standard with many founding partners that are large players in the microchip industry. If they are so wrong...why would so many be on board?

Where does your info come from? Wccftech? LOL!!!

Yeah...so how about you go make a thread about your predictions and talk about how ARM is going in every desktop PC next year...(then next year you can say it will be the year after, and so on, and so forth...)

Then you can talk out an orifice other than your mouth using marketing slides and PR blurbs about AMD with no real concrete info from anywhere to actually put your theories on...

 

[8350rocks]

whats really so great about maxwell? when i look at the difference in the gtx 970 and the 780 the 970 really just gets a win with a higher clock and a extra gig of vram. everything else just falls on the efficiency side.
i know your not talking about gaming but that is what is important to me without much regard to power draw and honestly its going to take a benchmark to tell the difference in a 970 and a 290 especially when you go higher than 1080p so if anything it shows that maxwell has a lean memory bus and they should have stuck with 384bit.

Thank you for throwing a logical observation and a small piece of sanity into this thread...

juanrga has such a wild imagination...he thinks ARM will overtake x86 for HEDT PCs, and people will be gaming on ARM computers soon.

 

[8350rocks]

However, improved branch prediction logic could easily squeeze more out of the available cache we have now. In fact, if AMD could improve that quite a bit, that would be some proverbial "low hanging fruit" in terms of the fact that they already will have the space dedicated to cache on the die anyway. In terms of actual execution, well they would have to come up with a better way to decrease missed predictions and increase efficiency in the pipelines. FAR easier said than done...however, in terms of improving CPU performance within the same or smaller footprint, branch prediction is a big area where you can make up a lot of ground, and increase power efficiency with the same stroke.

Precisely the way that AMD is going to reduce the branch misprediction penalty is not by improving the predictor accuracy but by reducing the pipeline depth, which has the side-effect of reducing considerably the maximum clocks achievable. That is why Opteron, FX based excavators are not coming and why any APu above 35W vanished in the air.

Rumor is that Excavator core tops at about 3GHz and that Carrizo CPU will be a step backward from Kaveri CPU. We will see.

What is funny is how AMD pursued a speed-demon CMT approach with Bulldozer and in each new iteration they are moving away. Steamroller was a step away from CMT with the double decoder, and now Excavator is a step away from speed-demon.

"Rumor is that..."

You have no sources...and mine are vehement that clock speed will improve over Kaveri.

Your rumors paint AMD as dying off tomorrow. Thankfully those same "rumors" have been around since Intel took the performance crown back from AMD years ago...because that is what Intel and NVidia want everyone to think.

If you believe all the "rumors" you hear...I have a bridge in brooklyn to sell you for $100.

 

[-Fran-]

No sure what are you really asking but I will try to answer.

Most commercial CPUs are based in the von Neumann paradigm, which is essentially a simple sequential paradigm where one thing is made at one time and as controlled by the program counter. Modern architectures (superscalar, VLIW) use 'tricks' to get hidden parallelism and speed up the serial stream, but that is all.

There are attempts to develop parallel paradigms, such as the dataflow model.

The dataflow computing model is known to overcome the limitations of the von Neuman paradigm by fully exploiting the parallelism inherent in programs. In the dataflow model, the operations are made when the data is available to the operands without any pre-determined order. Unlike the von-Neumann model, the dataflow model is neither based on memory structures that require inherent state transitions, nor does it depend on a program counter to sequentially execute a program.

However it has found difficulties for its practical implementation

http://en.wikipedia.org/wiki/Dataflow_architecture

Yes, that's the answer I wanted. Thanks Juan.

I did remember that from my Hardware Courses in University, that's why I know today parallelism is an illusion and not a *real* thing. I just couldn't remember why it was.

And yes, coherent memory structures are the base point for 99.9% of algorithms. They all assume serial processing in the end.

This thread was started as a temporary thread would die soon once the main was fixed. But nobody is doing it, I see.

The title is not adequate to make this thread a substitute of the other.

I think that a new thread with the title "AMD's Future Chips: News, Rumors & Reviews" could be launched and all us move to it. jdwii suggests some mod to rename this. Ideas? Agree/disagree?

Agreed.

Cheers!