Archived from groups: alt.comp.hardware.overclocking.amd (
More info?)
Josef Varela wrote:
>>> A64!=Opteron
>>>
>>> If the 939 platform is someday available for dual A64 it will kick
>>> ass.
>>
>> A64 == Opteron if you want anything but uniprocessor. Essentially
>> the same as with P4's and Xeons. And, to a lesser extent, XP's and
>> MPs.
>
> Even Celerons can do MP, it´s all about having a mainboard that
> supports it...
Sort of ... The only Celerons that could do SMP are the Mendocino Celerons.
Try dropping a couple of Coppermine Celerons into a board. They won't do
SMP. SOME celerons can do MP, but not all. Neither the Coppermine or
Tualatin Celerons can do SMP.
Back in the Good Old Days, SMP used to be entirely dependant on the board.
This was because 486's and the like had no SMP capability build in (save for
the #LOCK pin). All the SMP stuff was done in chipsets. ServerWorks or
whoever would spends a few million dollars designing a chipset that could
run multiple 486's, and then sell it in small quantities at large prices.
This all changed with the Pentium (IIRC), which actually had some built-in
support for SMP configurations. The main part was the APIC, which suported
interprocessor interrupts, among other things. So at this point, the chipset
makers could do away with a lot of the complex stuff that used to be in the
chipset, and use the on-CPU features instead. This then gave Intel/AMD the
capability to produce SMP capable or incapable CPUs, as if these new bits
weren't enabled, then the CPU could not do SMP (as there was little point in
a chipset maker adding this stuff to their chipset).
AFAIK, the first CPUs to suffer this fate were the Coppermine Celerons. All
CPUs prior to that could do SMP, regardless of what Intel sold them as.
Because the chipsets nowadays rely on SMP support from the CPU, there's no
way for a "SMP-disabled" CPU to do SMP. The exact same thing applies in the
AMD camp, though with the A32's you could re-enable this support.
On the A64 front, the Clawhammer has 2P capability built into it (but the
required HT links and actual SMP capability are not enabled). The Opteron
has 8-way (possibly more) capability built in, and how much is enabled
depends on how much you pay. I haven't heard anything about the SMP
capability or otherwise of the Newcastle or Sempron cores.
Sure, ServerWorks et al COULD come up with a chipset that enabled
SMP-disabled A64's to do SMP by doing all the stuff that's normally done in
the CPU in their chipset. However, the price point would be (significantly)
above current Opteron chipset prices, so would make no financial sense. So
don't get your hopes up.
> My old BP6 with bx chipset and 2x533 Celeron was the best bord I ever
> had. The VP6 can do MP new Celerons.
Umm, no it can't. The VP6 can't do ANY Celerons in SMP, Mendocino or
otherwise (google for "VP6 celerons").
--
Michael Brown
www.emboss.co.nz : OOS/RSI software and more
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