Extreme Overclocking: 10 Ryzen CPUs Under LN2

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I think some folks are unaware that there are bunches of AMD supporters who have tracked batch numbers for years, compared characteristics and properties by benching and tweaking, and shared 'sweet weeks' and manufacturing with enthusiasts.

Intel fans do the same thing but it seems less prevalent.

 

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Titan
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I haven't looked at CPU OC databases in over a decade. These things were hyperactive back in the P2/440BX days with the legendary Celeron 300 OCs to 600+MHz and already died down quite a bit by the time the P4 arrived.
 
...I haven't looked at CPU OC databases in over a decade. These things were hyperactive back in the P2/440BX days with the legendary Celeron 300 OCs to 600+MHz and already died down quite a bit by the time the P4 arrived.

Times have changed, fer sure. Clocking and voltage manipulation is 'baked-in' with modern procs -- as opposed to pencil mods and jumper pins to set the bus speeds.

Some folks still keep an eye on batch numbers (as the article demonstrates why) and I'm still guilty -- last went looking for 'Week 46 - Year 14' (made up number) FX-6350s that tended to clock to the moon at low volts. I seem to recall when Intel switched from solder to paste some enthusiasts went batch-looking for chips which ran cooler and clocked higher.

It's not fair to AMD (it's the cynic in me) but I'm thinking the Ryzen desktop chips are their initial 'dregs' this round with all the gravy going to Epyc and Threadripper. I'm thinking re-spins, new steppings (and Summit Ridge) are likely to bring more headroom to clocks, more consistency and even better performance.

I'll still keep an eye on batch numbers -- ever searching for those 'golden chips' in the lottery ...

:na:

 

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Titan
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That wouldn't surprise me at all. When I looked at the Zeppelin die images, I thought the 16 HSIO macros were one per PCIe lane but with TR/EPYC, it turns out that each of those macro is four lanes wide. One dead or malfunctioning HSIO macro and the chip loses its EPYC viability. One bad HSIO macro in the wrong place and it loses TR viability. There is also that matter of fitting so many cores in a relatively low TDP, which implies binning dies for the lowest operating power to keep cooling requirements within manageable bounds.
 
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