Question For the Wiz-Kids

[Dr_VinniGoombatz]

M.2 keying specs. speak in terms of PCIe lanes. My latest MB has M.2 sockets that are shared with the PCIe bus. IF, and this is hypothetical as the HW add-on configuration doesn't exist, I think. Could a PCIe x1 coexist on this "Shared" bus with an M.2 E keyed module configured to use the lanes not used by the PCIe x1 device? I would think so as the PCIe specs. speak of dynamic lane configuration.

 

[Eximo]

Not quite sure I fully understand the question.

Are you asking if say a M.2 PCIe 2x lane card was installed, could you then have another M.2 slot use the remaining lanes? Or if you could split the lanes coming off a 4x M.2 slot?

If so, I think the answer is no.

In general that is how the PCIe bus is divided up, 1x, 2x, 4x, or 8x, or 16x. If you built a bifurcation into an M.2 compatible card/cable, then maybe? Not sure why you would rather than just getting something like a PCIe expansion card with many M.2 slots.

Not sure E type really made it into the wild in any significant number.

 

[Dr_VinniGoombatz]

👌This was just a hypothetical. "In another life", I'm retired now, I had many a bus "adaption(s)" to "play with.

I was reading through the PCIe, SATA, M.2, ... specifications and noticed that all are PCIe-like logically. I thought at initialization since lanes are negotiated in SW one could "mortify" the physical connections and say, have various x1 lanes physically connected to different devices within the shared MB connectors. Now I'm thinking, as I've not reverse-engineered driver SW it may not be able to negotiate among different HW devices on the same PCIe, M.2 connector. That is, it's only smart enough to determine lane counts and active com lines. BUT! Oneee du Shadow knows what lurks in the inter sanctum of logic circuits.👍 Thanks for the response.

P.S. This would be a good driver SW add-on. I don't know how one would handle multiple usage of lanes when users oops the connections. Another opportunity for the chipset/CPU engineers to excel, right? OR, make it all the same form factor so when devices are connected data all you get in a per lane configuration.

 

[Eximo]

I have absolutely no idea what you are trying to say.

Pretty sure the limits of hardware and firmware in regards to PCIe bifurcation are already defined in the standards. And they would have to be adhered to for the standard to have any usefulness.

Hot swap standards for PCIe is already defined as well, though this doesn't always work perfectly in practice.