FSB Question

[ggarret1]

Nice article, very well writen and informative.

I have to apologize for my comments on asynchronous clocks. The links I found for “asynchronous clocks” all have to do with system components being out of phase (no system clock so they get out of sync). If I google asynchronous bus however, I see that asynchronous is used to refer to mem and cpu running at sub-multiples of the system clock.

 

[Crashman]

Of course you can't get more data through the memory than the CPU, that's why people saw little advantage to running PC133 at 133MHz on their 100MHz bus processors. How could they see any advantage at all? Higher clock speeds reduce cycle time, and CAS latency is measured in cycles. CAS3 at 133MHz is faster than CAS3 at 100MHz. That's just a little background BTW.

Anyway, the perfect match for a 533 bus P4 would be PC2100 in dual-channel mode. But when the 533 bus was in it's prime, dual channel did not yet exist for DDR SDRAM boards.

So back then people would typically use 533 bus P4's with PC2700 RAM in single-channel. PC3200 hadn't gone mainstream yet. That's a CPU bus of 133MHz x4, and a RAM bus of 166MHz x2. Obviously the RAM had less bandwidth than the CPU FSB.

Yet back then, a 533 bus P4 on PC2700 was still faster than a 400 bus P4 on PC2700. How could that be...when PC2700 in single-channel had less bandwidth than even the 400 bus P4? Isn't the limitting factor, PC2700, the same?

Well, sort of. That FSB from the CPU to the chipset also handled other types of transfers, transfers to local busses and ports like AGP. In fact, one of the main advantages added to AGP was direct access to the CPU without going through RAM. Of course RAM was still caching some stuff for the AGP card, mostly textures, hence there was also a setting called "AGP Aperture" to limit the amount of RAM that could be used as cache by the AGP.

Synchronous data rates are nice, but not always used. Synchronous clock rates between the CPU bus and RAM used to be required, but no more. And Intel uses a Quad Data Rate bus, which is properly but rarely labeled QDR, for their CPU.