News Grinding Off Ryzen 7000 IHS Seemingly Lowers Temps By 10 Degrees Celsius

[ravewulf]

I wonder if the thicker IHS could also be to accommodate the 3D V-Cache versions without needing to shave down the die with the extra cache on it. If they don't need to shave the die, they can use a thinner IHS and still take up the same vertical space.

 

[InvalidError]

I wonder if the thicker IHS could also be to accommodate the 3D V-Cache versions without needing to shave down the die with the extra cache on it. If they don't need to shave the die, they can use a thinner IHS and still take up the same vertical space.

Shaving the back of the die doesn't really have anything to do with height constraints, that could easily be accounted for by adjusting the IHS pocket machining accordingly. The reason they need to shave the back is because the base layer etching process cannot reliably create holes deep and narrow enough to go all the way through, so they create the vias as deep as they reasonably can, then shave the back to expose them. Making the wafers thinner to skip this step isn't an option either since they are already about as thin as they can slice and handle them.

 

[Johnpombrio]

There was an interesting chart about using a solid socket interface on the Raptor Lake CPUs here yesterday. It shows that the drops in temperatures were directly related to how much power was being drawn. Under normal loads and a sensible overclock, there was only a 2-3 degree difference in cooling (BTW, I got only a 2-3 degree drop in temp on my i7-12700K Alder Lake with a moderate overclock and air cooling.) With the HIGHEST power draw, it was closer to 10 degrees C. Probably the same holds true here. Under bleeding overclocks and heavy cooling options, yes, 10 degrees C drop in temps is possible, but for normal and sane enthusiasts, expect only a small drop in temps for a MUCH riskier delidding.

 

[bit_user]

DeBauer came up with offset-mount adapters to re-center the HSF over the CPU chiplet(s) instead of IHS and managed to shave a few extra degrees that way.

Does anyone know of an overlay showing where the chiplets are located within the package? I'm also looking for this info on Ryzen 5800X.

 

[bit_user]

So that's where I get my 30% # from. That "low "lip" area would get raised to the top of the IHS and be part of the Flat Contact Area between the IHS & CPU Cooler Flat Bottom Plate.

I had a question about that. If that low "lip" cuts into the footprint of AM4, why did they do it? Cost savings?

 

[Kamen Rider Blade]

I had a question about that. If that low "lip" cuts into the footprint of AM4, why did they do it? Cost savings?

AMD said it had to due with "Manufacturability" and getting it working with Automated Assembly.

Maybe that's true, maybe they were on a limited time crunch, who knows what the real truth is.

AM4 is a giant Rectangle that is almost 100% sealed, I don't see why can't make a similar version, but with small cut-outs on the side to account for the SMD Capacitors/Transistors that are near the edge of the PCB & have a small cut-away for the retention mechanism tabs.

 

[LuxZg]

Bit of a fake news. Watching video he shows temps a bit too briefly by the end, but even he says lapping only got him 5C lower, rest is the new paste. So for 5C certainly not worth the trouble, and that 5C could be largly attributed to just a better overall finish after lapping, same as with eg Intel AL.

 

[InvalidError]

Does anyone know of an overlay showing where the chiplets are located within the package? I'm also looking for this info on Ryzen 5800X.

On 7000, three sides have SMDs in it and the CCDs are almost right along the edge opposite to the cut-outs that have no SMDs. If AMD kept the same substrate markings as AM4 and the same relative positions, then that would be the notched side opposite to the "pin 1" corner marked with a triangle.

Edit: intuitively, I would have expected the IOD to be on the DIMMs' side since that is where the bulk of IO pins are needed and would put the CCDs closest to the VRM but looking at AM4 socket and substrate pictures, the "pin 1" corner is on the bottom-left, which puts everything the other way around. On AM5, things have been rotated 90 degrees clockwise, which puts the CCDs closest to the PCIe slots. I wonder what sort of esoteric engineering considerations went behind this seemingly still sub-optimal configuration.

I had a question about that. If that low "lip" cuts into the footprint of AM4, why did they do it? Cost savings?

The lip is so the LGA retention latch can apply pressure to the IHS without interfering with the HSF, same as Intel's LGA socket.

 

[-Fran-]

Related:

View: https://www.youtube.com/watch?v=JH1JkkmG_qQ


Interesting findin the harvesting strategy AMD chose wth the 7600X and potentially 7700X. Could you unlock the second CCD? Maybe a scond "X3" generation with a free core (CCD in this case?). Failed X3D attempt? Interesting options there, but to the point of that, you can even passively cool the 7600X while delidded. Holy cow.

Regards.

 

[InvalidError]

Interesting findin the harvesting strategy AMD chose wth the 7600X and potentially 7700X. Could you unlock the second CCD? Maybe a scond "X3" generation with a free core (CCD in this case?). Failed X3D attempt? Interesting options there, but to the point of that, you can even passively cool the 7600X while delidded. Holy cow.

My guess is the CPU was initially supposed to be a 7900/7950 but one of the CCDs failed somewhere between on-wafer testing and substrate assembly testing. Could be something like a bad joint in the IOD-substrate-CCD path.