HKEPC: AMD's 65nm at 5th December

[toasty2]

Not really. Before the C2D's, Intel was releasing processors that could heat your house...

Also, if you look at a place like newegg, if you find a dual core processor from Intel that is at a similar price to the X2 3800+, you will see that the X2 is much better in benchmarks. Look at the CPU charts.

 

[dasickninja]

The Northwood CPU's were okay. The Prescots were different archs.

 

[toasty2]

I was mainly talking about processors like the Pentium D 805. Even at its low performance, its one of the hottest things in existence as far processors.

 

[dasickninja]

Let me be the first to say it. Netburst in all its incarnations was suckass. One Netburst was crap, two Netburst was condensed extra grade a crap with a soda on the side. Three would have been just too much crap. But thats all in the shitty past.

 

[accord99]

I agree its depressing, but AM2+ should be really worthwhile. No matter how high intel can get their cpus to overcluck or how mnay cores they add, nothing will be able to keep up with a 4ghz hypertransport bus. That'l make intel users wish they never spent even 180 on a 6300

A faster HT bus will have no impact on desktop performance.

 

[evilr00t]

Not really.

What?
If you're replying to a "reputable", I don't think AMD is any more reputable than Intel, nowadays. The nForce chipsets are as stable as the Intel ones.

A lot of corporations trust Intel more than they trust AMD, since AMD's past chipsets (glares at VIA) tarnished their reputation.

Also, if you look at a place like newegg, if you find a dual core processor from Intel that is at a similar price to the X2 3800+, you will see that the X2 is much better in benchmarks. Look at the CPU charts.

Don't see what you're saying.
The E6300 smokes the X2 3800+ in all benchmarks, and it's only $21 more than the 3800+.

nothing will be able to keep up with a 4ghz hypertransport bus.

Wrong, apples and oranges. Processor performance != hypertransport bus clock speed. It's like comparing instruction retire rate to bandwidth, or comparing light years to seconds.

 

[accord99]

if intel is doing increase on an fsb/cache,i dont see why ht wouldnt boost amd.

On the desktop with 1 socket, the HT bus only links the CPU to the motherboard chipset, which is not a bottleneck.

 

[lyssword]

From what I heard, amd constantly improves their version, and as many ppl know, their earliest a64 chips were not great overclockers, they add tweaks as they go along. 65nm may overclock better, but amd is more confident in their 90nm process design, thats why high mhz chips still stay 90nm, because they perfected that design. As they manufacture more and more 65nm's, there will undoubtedly come a point where they perfect 65nms to run at higher clock than 90nm.
My 2 cents..

 

[accord99]

if you widened that bus wouldnt it increase speed?or is it just walled at the cpu speed.i honestly dont know. 😳

It's like when ATA-133 (or SATA-300) was released, the bandwidth was increased but offered no real improvement in performance because the existing bandwidth was enough for existing traffic.

so htt has nothing to do with memory?

Not on a single socket. The memory connects to the on-die memory controller which connects directly to the CPU at CPU speeds.

and so what would it need to catch up with c2d?

New core like K8L or 30% increase in clock speed.

 

[accord99]

HTT 3.0 is for 4S and higher systems as the current HTT is too-low bandwidth and has too few links for effectively scaling past 4 sockets.

What AMD needs to take on Core 2 Duo on the desktop is to have similar technologies, better prefetching to reduce latencies even more, memory disambiguation, faster and wider caches, etc.

 

[joset]

What AMD needs to take on Core 2 Duo on the desktop is to have similar technologies, better prefetching to reduce latencies even more, memory disambiguation, faster and wider caches, etc.

Well, that would make an AMD processor out of an Intel one, now wouldn't it?! 😀


Cheers!

 

[endyen]

and so what would it need to catch up with c2d?

It looks to me like the biggest difference between the two, is SSE. AMD has never been able to get good functionality from Intel's extensions.
Then again, with ATI on board, they may be able to solve that little problem.

 

[qcmadness]

HTT 3.0 is for 4S and higher systems as the current HTT is too-low bandwidth and has too few links for effectively scaling past 4 sockets.

What AMD needs to take on Core 2 Duo on the desktop is to have similar technologies, better prefetching to reduce latencies even more, memory disambiguation, faster and wider caches, etc.

AMD just don't need very good prefetching as the CPU L2 sizes are way too small. Also they have a large L(n+1) cache - on-die memory controller.

Wider cache and wider execution units definitely help also.

 

[endyen]

It may be the flu talking, but didn't Ruis say earlier this year, that 65 nanos would include SiGe and NiSi?
Not that that would give first run chips much, but the improved IdSat should come in handy at some point no?

 

[qcmadness]

and so what would it need to catch up with c2d?

It looks to me like the biggest difference between the two, is SSE. AMD has never been able to get good functionality from Intel's extensions.
Then again, with ATI on board, they may be able to solve that little problem.

SSE execution should be more efficient with K8L.
But it is still a spectulation.

 

[qcmadness]

It may be the flu talking, but didn't Ruis say earlier this year, that 65 nanos would include SiGe and NiSi?
Not that that would give first run chips much, but the improved IdSat should come in handy at some point no?

Source??????

I want to know more about this too

 

[endyen]

Intel would love to have AMD's latency numbers. IIRC, Intels chips are about 60%+ slower than AMD's in this department.

 

[qcmadness]

so why is amd
prone to memory latency?cache amt is nothing i know that.
wider cache meaning more info in and out of cache via?the execution units?

The latency measurements by different programs have different characteristics.

K8's L2 is only 128-bit wide while Core Arch's L2 is 256-bit wide.

More decoding units should be added.

 

[qcmadness]

hmmm,ok i am getting it a bit more.

why doesnt amd increase the decoders size?the cache width and the execution bus width?

and if thats all it takes to catch up to c2d why havent they done it?
this isnt the whole probability scenario here,these are bits and pieces of it.

they cant make an intel cpu without a license,so their approach must be different and we may guage speed increase in one chip from one set of rules and then make another set for amd.

Even improving the decoder and cache width, AMD's architecture approach is still entirely different from Intel's.

What K8L has improved:
1. L3 Cache
2. 1 cycle SSE execution
3. Faster Hypertransport bus
4. Better pre-fetching alogarithm

 

[qcmadness]

a prefetch algorhythm is a time based electronic signal based on what part of the architecture?the on die mem controller?

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2768&p=3
http://www.xbitlabs.com/articles/cpu/display/amd-k8l_2.html

 

[papi4baby]

I think too many people are expecting miracles out of AMD's 65nm chips coming out. It will be a big dissapointment once they see it is the same chip as the 90nm. It will be a while before AMD can actually get performance out of 65nm. As of right now they just need to reduce their manufacturing cost.

 

[qcmadness]

I think too many people are expecting miracles out of AMD's 65nm chips coming out. It will be a big dissapointment once they see it is the same chip as the 90nm. It will be a while before AMD can actually get performance out of 65nm. As of right now they just need to reduce their manufacturing cost.

It is natural for AMD to be conservative in process advancement.

They cannot bear any failure in process advancement.

 

[gOJDO]

hmmm,ok i am getting it a bit more.

why doesnt amd increase the decoders size?the cache width and the execution bus width?

and if thats all it takes to catch up to c2d why havent they done it?
this isnt the whole probability scenario here,these are bits and pieces of it.

they cant make an intel cpu without a license,so their approach must be different and we may guage speed increase in one chip from one set of rules and then make another set for amd.

Even improving the decoder and cache width, AMD's architecture approach is still entirely different from Intel's.

What K8L has improved:
1. shared L3 Cache
2. 1 cycle SSE execution
3. Faster Hypertransport bus
4. Better pre-fetching alogarithm
5. 256bit L1/L2 width & two independend 128bit loads/stores per cycle
6. two independend ODMCs

 

[joset]

It may be the flu talking, but didn't Ruis say earlier this year, that 65 nanos would include SiGe and NiSi?
Not that that would give first run chips much, but the improved IdSat should come in handy at some point no?

😀

He (Ruiz) was probably quoting IBM-adapted-to-AMD process (didn't read that interview, anyway); but, AMD's 65 node will remain very different from Intel's in more than a thousand ways, the most evidenced being SOI+4 stressors vs Bulk+1 stressor. That's what is really amazing: Intel's still keeping the lead with an 'outdated' process, with relatively small changes, while AMD's still 'not getting there', with a much more 'fashionable' technology; sounds like magic... but it's much less than that.


Cheers!

 

[joset]

hmmm,ok i am getting it a bit more.

why doesnt amd increase the decoders size?the cache width and the execution bus width?

and if thats all it takes to catch up to c2d why havent they done it?
this isnt the whole probability scenario here,these are bits and pieces of it.

they cant make an intel cpu without a license,so their approach must be different and we may guage speed increase in one chip from one set of rules and then make another set for amd.

Even improving the decoder and cache width, AMD's architecture approach is still entirely different from Intel's.

What K8L has improved:
1. shared L3 Cache
2. 1 cycle SSE execution
3. Faster Hypertransport bus
4. Better pre-fetching alogarithm
5. 256bit L1/L2 width & two independend 128bit loads/stores per cycle
6. two independend ODMCs

I'm not that knowledgeable about architectures but, from what I've been able to grasp, some points are still somewhat 'inaccurate' or, better, they don't tell the whole truth (as always):

1. Why a shared, 'big' & upgradeable (in future revs) L3 cache, instead of a bigger, shared L2 cache (and, intel did not invent the 'shared cache' approach); how well will it compensate for the added latency? (it's closer to RAM but farther from the execution units);

2. This is a tweak I believe Intel will not have much trouble dealing with, in its own future architectural tweaks; however, these are multimedia/vector processing improvements; not 'mere' improvements but not decisive either, overall performance-wise;

3. AMD's exclusive;

4. "Better pre-fetching algorithm"; how better & how does it work?

5. "256bit L1/L2 width & two independend 128bit loads/stores per cycle"; but, no memory desambiguation, I guess, since L2 is not shared... so much for "two independend 128bit loads/stores per cycle" effective (best case scenario) capability; or, am I wrong?

6. AMD's exclusive; will the IMCs compensate for the L3 added latency?

This last point (as well as the whole 'memory' issues) might be a bonus for >4P set ups but... will it show as performance benefits in more restrict configurations?


Cheers!