News Huawei reportedly facing bad AI chip yields for processors made at Chinese fab SMIC: Report

izmanq

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zsydeepsky

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hmm, is this fact, or just opinion, huawei is selling all those large amount of mobile phone with 20% yield ?


the yield goes down as chip size grows, for a Chip that is as large as 456mm^2, 20% yield isn't bad actually.

as this graph represents:
800px-monolithic_design_vs_chiplet_yield.png

source: https://en.wikichip.org/wiki/chiplet

Huawei's Kirin 9000S has a die size of 107mm^2, so naturally it will have maybe 3X better yield rate than this gigantic Ascend 910B chip, so if 910B can have 20% yield, then Huawei can definitely mass produce their phone SoCs with 60%+ yield, which is totally fine.
 

zsydeepsky

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with open sources, at least Apple had their A17 chips with ~55% yield with TSMC 3nm node, but that was 1 year ago.


with that yield rate (obviously not ideal for TSMC, compared to other nodes), TSMC's price per wafer upped by 22% six months later, so I would guess that even if yield improves it would still be lower than their initial expectation.

https://www.tomshardware.com/tech-i...growth-now-comes-from-more-expensive-products

I couldn't find the size of A17 chip...but A15, which is 107 mm^2, is almost identical to Kirin 9000S. so if A17 shares the same size, then it's safe to say that Huawei enjoys a similar yield compared to Apple.
 
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with open sources, at least Apple had their A17 chips with ~55% yield with TSMC 3nm node, but that was 1 year ago.


with that yield rate (obviously not ideal for TSMC, compared to other nodes), TSMC's price per wafer upped by 22% six months later, so I would guess that even if yield improves it would still be lower than their initial expectation.

https://www.tomshardware.com/tech-i...growth-now-comes-from-more-expensive-products

I couldn't find the size of A17 chip...but A15, which is 107 mm^2, is almost identical to Kirin 9000S. so if A17 shares the same size, then it's safe to say that Huawei enjoys a similar yield compared to Apple.
That’s TSMC’s original N3 process which half way through development realized was a dead end and they stopped all further refinement after reaching initial production, essentially TSMC only released N3 to fulfill contract obligations with Apple. N3E was a ground up redesign and solved many yield problems encountered with the original N3. The original risk start yield rate for N3E in 2022 was >80%, 2 years later the yield rate is ~95%.
https://www.tomshardware.com/news/leaked-tsmc-slide-shows-n3e-yields-progressing-ahead-of-plan
 
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with open sources, at least Apple had their A17 chips with ~55% yield with TSMC 3nm node, but that was 1 year ago.


with that yield rate (obviously not ideal for TSMC, compared to other nodes), TSMC's price per wafer upped by 22% six months later, so I would guess that even if yield improves it would still be lower than their initial expectation.

https://www.tomshardware.com/tech-i...growth-now-comes-from-more-expensive-products

I couldn't find the size of A17 chip...but A15, which is 107 mm^2, is almost identical to Kirin 9000S. so if A17 shares the same size, then it's safe to say that Huawei enjoys a similar yield compared to Apple.
Also you can’t really compare the yield rates of SMIC 7nm with TSMC 3nm as 3nm is bleeding edge technology and 7nm is approaching legacy status.
 
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zsydeepsky

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Also you can’t really compare the yield rates of SMIC 7nm with TSMC 3nm as 3nm is bleeding edge technology and 7nm is approaching legacy status.
you think that SMIC can't improve their yield as well?
just pointing out that whatever Huawei & SMIC were doing, they were doing them quite normally.
you don't have to bring your political sentiment into this.
 
you think that SMIC can't improve their yield as well?
just pointing out that whatever Huawei & SMIC were doing, they were doing them quite normally.
you don't have to bring your political sentiment into this.
I didn’t, but you are clearly biased enough to think I was. Facts are facts, and comparing yield rates of 3nm to 7nm is apples to oranges.
 

KnightShadey

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First, people need to stop getting distracted by phone chips.
They only reference Kirin as it's also on Huawei's 7nm node. Getting side-tracked by cellphones is ridiculous, and an obvious effort to distract from the failure of SMIC

Phone chips =/= HPC & AI accelerator chips, dramatic size difference and associated defects/yield/total chips beyond just node.
Also, 7nm =/= 5nm (of H100 & M250) nor 3nm of cellphone chips (or even Epyc).

What is tsmc/samsung etc yielding for similar size cpus?

Comparing nodes beyond those used isn't practical either as a direct comparison or for ramp-up. The difficulty increases with the shrink, complexity and size, so no using Apple & TSMC's first gen 3nm low power process for cell chips as an example of the challenges is not relevant. It would've been far more relevant to at least compare the 7nm yields of TSMC's mature process rollout (as this is Huawei's 2nd Gen according to the article not first), or even current 5nm (which had an even better rollout than 7nm @ TSMC as IT IS relevant since it is the current Ai chip node for the products Huawei is attempting to replace/replicate, even though nV and AMD are moving on to 3nm and likely 2nm by the time SMIC's chips see wide rollout).

What Zsky's graph above failed to show is defect rate improves over time.

20% yield is low, even adding some small # of useable chips of the 4/5 with defects is still not good, leaving 20% + X useable defects that need to be bined.

This can improve, but for 2nd Gen, that's not great. Even a relatively high defect rate of 0.3 should achieve a typical 30% yield for 450mm2 chips (about 36 unblemished chips per wafer 84 with defects [designing to avoid wasted partials in the equation]).
With 2nd Gen TSMC 7nm at initial 0.2 defect rate yield is 45% /52 good chips, and early maturity starts to go below 0.1 which yields 65% about 78 chips per wafer and improves fractionally until it reaches current 90+% yield. According to n5 supposedly achieve 0.1 D0 at high volume production with a quick trend lower. See graphs below for details regarding TSMC's process rollouts.

Second, to Z, this isn't politics, it's simple math based on the information provided.

The 'political'/production reality that goes against TSMC's economic constraints and path, is that the gov't is going to pay SMIC to make it happen regardless, meaning SMIC don't have the same viability concerns based on price/cost customer equilibrium challenges TSMC has. SMIC just need to reach volume / effectiveness of producing a part that can substitute for the A100 as intended. So yields/defects have different implications than someone trying to compete at selling a node's efficacy/efficiency to customers who have options even within TSMC.
Other countries also provide support to their chip industries, directly/indirectly so that's nothing new, but in this case there are little/no alternatives the domestic market can turn to, and it is seen as a necessity. So yield/defect rate isn't the same level determinant of success when there are non-economic factors involved in achieving the goal. Whereas TSMC and it's customer would just switch to another node... or another Fab if yields were so poor.
However, LONG TERM, SMIC needs to get much better at this or they will just fall further behind, not just stay 4yrs/2nodes behind TSMC (or intel).


Manufacturing%20Excellence.mkv_snapshot_02.11_%5B2020.08.25_14.16.22%5D.jpg


Advanced%20Technology%20Leadership.mkv_snapshot_03.02_%5B2020.08.25_14.15.08%5D.jpg
 

zsydeepsky

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ah, I like people who talk with data & graphs, so thanks for the reply @KnightShadey
my vision towards semiconductors for China overall is not limited to comparisons between "x-nm"s, after all, chip productions are really a system engineering question, it's all about how to maximize what you have.
Ascend 910B is an inconvenient edge case for Huawei, they designed the 910 series chip while they had access to TSMC, (the same goes for the Kirin 9000S), so they naturally would reach their best economic balance point with TSMC nodes. they are using old designs in SMIC only because they had no time to change chip designs while rushing towards their first 7nm mass production capability.

so, what happens next will be changing their chip designs to fit SMIC nodes. which Huawei has already done...6 months after Kirin 9000s, they launched Kirin 9100, same SMIC node, lower power consumption with slight higher performance.

same thing happened before, in the US, that was AMD and its Zen chiplet architecture. when AMD designed their first Ryzen CPU they assumed that they could only get worse yields or nodes (compare to Intel) with Global Foundries, but with chiplet design they can get better production yields since each CCD is smaller. I assume that Huawei would also adopt the same strategy (phone socs & gpus). in recent Huawei Developer Conference, they even showed their mass GPU grids with mass parallelism and elastic Vram, and even showed trillion-parameter AI models trained on them.

different restrictions lead to different engineering choices, that's my view.

besides, semiconductor nodes improvements are diminishing anyway, like Apple A17 (TSMC 3nm) showed almost identical power efficiency compared to A16 (TSMC 4nm). I also estimate Huawei being always 2 nodes behind TSMC for the next decade, but with proper engineering, that would be sufficient to allow them to stay in the market and profit from it without gov funding. in fact, thanks to the embargo of Nvidia gpus they are already earning billions by selling A100 equivalent products (Ascend 910B), and they are about to launch 910C soon. interesting things are about to unfold in the next few months.

LONG TERM wise, the fact that they (Huawei, SMI, or the entire Chinese semiconductor sector) are still surviving has much more impact than the 2 nodes behind TSMC.


a bit long, also a bit off-topic. so a conclusion of my points on this news about "910B yield":
- 20% yield for 910B: so so, not good, but not too bad either
- phone soc yield: good enough.
- therefore, SMIC & Huawei are in healthy condition since they are earning profits in the market, and the overall Chinese tech industry is unhindered because these two provided what they need.
- 910C yield would be a much more interesting thing to observe.
- also, yield for Huawei's next phone soc.
 
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shady28

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From the article:
Unlike TSMC and Samsung Foundry, which use EUV lithography tools to make chips using advanced process technologies, SMIC has to rely on multi-patterning and DUV lithography machines.

Sounds like they are basically doing the same thing Intel did with its "10nm" and "Intel 7", only intel got a lot better at it after its 2019 failure. Not only did it take them about 4 years to get to their first try with 7nm in 2019, it took about 2 more years before they perfected it (giving us Alder Lake in 2021).

I'm sure SMIC will improve, but like Intel it will take some time. Still, 7nm-class is probably the best one can do from a practical standpoint using DUV and multi-patterning.
 
From the article:


Sounds like they are basically doing the same thing Intel did with its "10nm" and "Intel 7", only intel got a lot better at it after its 2019 failure. Not only did it take them about 4 years to get to their first try with 7nm in 2019, it took about 2 more years before they perfected it (giving us Alder Lake in 2021).

I'm sure SMIC will improve, but like Intel it will take some time. Still, 7nm-class is probably the best one can do from a practical standpoint using DUV and multi-patterning.
They can probably eke out a 5nm process with absolutely poor yields by adding chemical etching into the mix.
 

shady28

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They can probably eke out a 5nm process with absolutely poor yields by adding chemical etching into the mix.

Not practical to go past 7nm using DUV, at least not for any volume. You can even go lower than 7nm, down to 5nm and lower probably, if willing to accept very low yield - which would be likely for some applications (military probably). It's ok to get one chip per wafer in some circumstances, and perhaps one chip for 10 or 20 wafers in some situations. Just not for consumers given the wafers cost ~$10K.

SMIC is probably still 2 years away from where Intel was with its DUV 7nm-class nodes in 2021, which produced Alder Lake. SMIC's 7nm node sounds a whole lot like Intel's "Ice Lake" node in 2019, which had poor yields and high power usage for a 7nm class node. So 1-2 years from mass production competitive 7nm.
 

shady28

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ah, I like people who talk with data & graphs, so thanks for the reply @KnightShadey
my vision towards semiconductors for China overall is not limited to comparisons between "x-nm"s, after all, chip productions are really a system engineering question, it's all about how to maximize what you have.
Ascend 910B is an inconvenient edge case for Huawei, they designed the 910 series chip while they had access to TSMC, (the same goes for the Kirin 9000S), so they naturally would reach their best economic balance point with TSMC nodes. they are using old designs in SMIC only because they had no time to change chip designs while rushing towards their first 7nm mass production capability.

so, what happens next will be changing their chip designs to fit SMIC nodes. which Huawei has already done...6 months after Kirin 9000s, they launched Kirin 9100, same SMIC node, lower power consumption with slight higher performance.

same thing happened before, in the US, that was AMD and its Zen chiplet architecture. when AMD designed their first Ryzen CPU they assumed that they could only get worse yields or nodes (compare to Intel) with Global Foundries, but with chiplet design they can get better production yields since each CCD is smaller. I assume that Huawei would also adopt the same strategy (phone socs & gpus). in recent Huawei Developer Conference, they even showed their mass GPU grids with mass parallelism and elastic Vram, and even showed trillion-parameter AI models trained on them.

different restrictions lead to different engineering choices, that's my view.

besides, semiconductor nodes improvements are diminishing anyway, like Apple A17 (TSMC 3nm) showed almost identical power efficiency compared to A16 (TSMC 4nm). I also estimate Huawei being always 2 nodes behind TSMC for the next decade, but with proper engineering, that would be sufficient to allow them to stay in the market and profit from it without gov funding. in fact, thanks to the embargo of Nvidia gpus they are already earning billions by selling A100 equivalent products (Ascend 910B), and they are about to launch 910C soon. interesting things are about to unfold in the next few months.

LONG TERM wise, the fact that they (Huawei, SMI, or the entire Chinese semiconductor sector) are still surviving has much more impact than the 2 nodes behind TSMC.


a bit long, also a bit off-topic. so a conclusion of my points on this news about "910B yield":
- 20% yield for 910B: so so, not good, but not too bad either
- phone soc yield: good enough.
- therefore, SMIC & Huawei are in healthy condition since they are earning profits in the market, and the overall Chinese tech industry is unhindered because these two provided what they need.
- 910C yield would be a much more interesting thing to observe.
- also, yield for Huawei's next phone soc.

They're going to be stuck at 7nm class nodes for a long time unless they steal tech from AMSL. That's not going to be good enough in a few years. There are multiple 2/3/5nm class fabs coming online in that time, and at that point they'll be in a world of hurt as even the cheapest phones from their competitors will be significantly better.
 
Not practical to go past 7nm using DUV, at least not for any volume. You can even go lower than 7nm, down to 5nm and lower probably, if willing to accept very low yield - which would be likely for some applications (military probably). It's ok to get one chip per wafer in some circumstances, and perhaps one chip for 10 or 20 wafers in some situations. Just not for consumers given the wafers cost ~$10K.

SMIC is probably still 2 years away from where Intel was with its DUV 7nm-class nodes in 2021, which produced Alder Lake. SMIC's 7nm node sounds a whole lot like Intel's "Ice Lake" node in 2019, which had poor yields and high power usage for a 7nm class node. So 1-2 years from mass production competitive 7nm.
I would say SMIC’s 7nm process is not practical given the already poor yields, but SMIC, based on their published research, is attempting to use chemical etching to overcome the resolution limits of DUV for their 5nm process. And since SMIC is being heavily subsidized, practicality isn’t important to them.
 

zsydeepsky

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They're going to be stuck at 7nm class nodes for a long time unless they steal tech from AMSL. That's not going to be good enough in a few years.
well, Huawei is about to launch their new Mate series in one month or two.
Rumors are that they are already beyond 7nm.
but we can just wait and see. ;)

and at that point they'll be in a world of hurt as even the cheapest phones from their competitors will be significantly better.

also, Huawei is releasing their new Harmony OS as well, on Chinese social platforms we are already seeing some performance comparisons between Android & HMOS, ~20% CPU performance boost just by upgrading to the new OS. which put their last-gen 7nm processors outperformed other phones that use 4nm Snapdragon 8 Gen2.

so, cheap Android phones will have a very hard time to compete with Huawei phones in future.
 
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well, Huawei is about to launch their new Mate series in one month or two.
Rumors are that they are already beyond 7nm.
but we can just wait and see. ;)



also, Huawei is releasing their new Harmony OS as well, on Chinese social platforms we are already seeing some performance comparisons between Android & HMOS, ~20% CPU performance boost just by upgrading to the new OS. which put their last-gen 7nm processors outperformed other phones that use 4nm Snapdragon 8 Gen2.

so, cheap Android phones will have a very hard time to compete with Huawei phones in future.

Can you provide a source for “~20% CPU performance boost”? Because all I’m finding is “based on app opening times” which can be artificially boosted and thus is not a reliable indicator of CPU performance.
 

zsydeepsky

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Can you provide a source for “~20% CPU performance boost”? Because all I’m finding is “based on app opening times” which can be artificially boosted and thus is not a reliable indicator of CPU performance.

for example, this one, using the video exporting speed as a comparison:

https://www.bilibili.com/video/BV1odsdeuE9o

in case you didn't get the Chinese voiceover...
Huawei Pura 70, with Kirin 9010 (7nm), same raw video, same video export setting.
Huawei Pura 70, Harmony OS 4.2 (AOSP 12): 95 seconds
Huawei Pura 70, Harmony OS Next alpha (not Android): 70 seconds
OnePlus 12 (Snapdragon 8 Gen 3, Android 14): 65 seconds
 
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for example, this one, using the video exporting speed as a comparison:

https://www.bilibili.com/video/BV1odsdeuE9o

in case you didn't get the Chinese voiceover...
Huawei Pura 70, with Kirin 9010 (7nm), same raw video, same video export setting.
Huawei Pura 70, Harmony OS 4.2 (AOSP 12): 95 seconds
Huawei Pura 70, Harmony OS Next alpha (not Android): 70 seconds
OnePlus 12 (Snapdragon 8 Gen 3, Android 14): 65 seconds
Okay thanks, OS Next looks very promising for Huawei, but this just makes me wonder if the Huawei pura 70 could run current android 14, what the score would be against OS next? Because really this study just shows that Huawei customized android 12 is slower than OS Next.

The OnePlus 12 result is not directly comparable since it’s a different phone with different components so the 30 second difference could be due to the phone and not any improvement between android 12 and 14 for all we know.