Question If I Reduce Memory Frequency, Does Latency Automatically Decline?

[jaydub868]

Greetings. I want to build a PC with an Arrow Lake CPU and a Z890 motherboard. This particular motherboard can accommodate DDR5 native memory frequency of 5600MHz and an overclock frequency of 8666MHz. I'm looking at buying one of two G. Skill 16GBx2 dual channel kits: 1) 5600MHz with CAS latency of 28 which is 10.0 nanoseconds, or 2) 7800MHz with CAS latency of 36 which is 9.23 nanoseconds. If I opt for the 7800MHz modules, but decide later to set the frequency at 5600MHz to avoid overclocking, will the motherboard automatically assign lower latency numbers that align more closely with the 5600MHz modules, or would I have to make trial and error manual adjustments to get the latency down? The motherboard is an ASRock Z890 Pro RS WiFi White LGA 1851 ATX. Thanks.

 

[Misgar]

When you change the memory clock frequency, the BIOS checks the SPD chip and selects the appropriate timings. Sometimes the BIOS tweaks a few settings so they might not exactly match the SPD settings.
https://en.wikipedia.org/wiki/Serial_presence_detect

If there are multiple SPD entries for one clock speed, the BIOS will normally select the fastest (tightest) settings. Higher clock speeds give you greater memory bandwidth. Latency is simply the time between actioning a request and the time when the data becomes ready.
https://en.wikipedia.org/wiki/Memory_latency

 

[jaydub868]

Does it seem likely that the SPD entries for latency in the 7800MHz memory module running at 5600MHz would be as quick or quicker than the SPD entries for latency in the 5600MHz module running at 5600MHz?

 

[Unolocogringo]

The latency of the modules is already lower when running at 7800. AND you have MORE bandwidth.
My option for you is to see how low of a cas latency you can achieve at 7800.
Less latency and faster memory. 34/44/44 would be my objective with that kit.
Best of both worlds.
Why buy high binned memory chips to run them at default jedec speeds.
Color me confused?

 

[jaydub868]

I wouldn't probably run 7800 rated modules at 5600. I was just wondering if I did run it at 5600, would CAS latency remain unchanged at 36. It sounds like if I did run it at 5600, the SPD would force a lower latency number in synch with the relaxed frequency.

 

[Misgar]

1) 5600MHz with CAS latency of 28 which is 10.0 nanoseconds, or 2) 7800MHz with CAS latency of 36 which is 9.23 nanoseconds.

I'm not a memory expert but I'd argue the Latency (measured in nanoseconds) does not change hugely between 5600MT/s where it's 10.0ns and at 7800MT/s where it's 9.23ns. If you run the Memory Latency test in Aida64 at various SPD frequencies, you see roughly similar results.

As an electronics engineer, I'm using the Wiki definition of latency as the time between setting up a request for data and that data being made available on the bus, not the number of clock cycles in the CL setting.

To quote from Wiki:
Latency should not be confused with memory bandwidth, which measures the throughput of memory.
https://en.wikipedia.org/wiki/Memory_latency
CL and many of the other timings held in SPD are measured in clock cycles, not nanoseconds. There is a direct equivalence between the DDR memory clock frequency (MHz) plus the number of clock cycles specified by CL(CAS) and the latency in nanoseconds.

Latency has an absolute value measured in units of time, in this case nanoseconds.
CL(CAS) is merely a number of clock cycles, but without knowing the clock frequency you cannot guess the latency from just the CL(CAS) value. Of course we normally know the clock frequency as well as CL, but without both values, we don't have the true latency in nanoseconds.

You need more clock cycles at a higher frequency to maintain the same latency, but fewer clock cycles at a lower frequency (hence the automatic changes in CL and other timings).

CL(CAS) is set in the BIOS by the SPD to 28 clock cycles at a true memory clock of 2800MHz (half of 5600MT/s Double Data Rate) and 10.0ns latency.

Similarly, CL(CAS) is set in the BIOS by the SPD to 36 clock cycles at a true memory clock of 3900MHz (half of 7800MT/s Double Data Rate) and 9.23ns latency.

Note: The latency doesn't change a great deal. For your DIMMs, I'd expect latency to sit around 9 to 10ns. Try measuring latency yourself at different XMP settings with Aida64.

What does change appreciably when you increase the clock rate is the overall memory bandwidth and this is far more important than worrying about latency.

To quote from Wiki:
Memory bandwidth is usually expressed in units of bytes/second
https://en.wikipedia.org/wiki/Memory_bandwidth

Increased bandwidth is usually beneficial. Whether or not your apps make good use of extra bandwith is different matter. The graph below shows the effect of increasing memory speed (and hence bandwidth) on a Ryzen 7950X and an Intel i9-13900K.

It sounds like if I did run it at 5600, the SPD would force a lower latency number in synch with the relaxed frequency.

True. When you change the XMP memory clock rate in the BIOS, it looks up the tables in SPD and chooses what it thinks are the most appropriate setting for CL and all the other Primary, Secondary and Tertiary settings, of which there are many.

As you increase the XMP speed, the BIOS will select larger values of CL, etc. The main disadvantage of running high XMP frquencies is potential system instability, more heat and possible long term effects of increasing the voltage on the RAM and the CPU's Integrated Memory Controllers. In addition, electromigration effects increase when you overclock CPU or RAM which can lead to deterioration in critical components. It might take years before you notice any negative effexts,
https://en.wikipedia.org/wiki/Electromigration

I find Aida64 handy for viewing the SPD tables, or you can use CPUID's CPU-Z.

Best of luck with your overclocking adventures.

 

[gskill support]

Default SPD setting will attempt one of the SPD profiles. Some motherboards have 'AUTO OC' feature that may attempt to tighten timings if enabled (generally not recommended). In most cases, XMP Profile timings are more aggressive than SPD profiles anyway, so if you wish to run a lower DRAM Frequency, you can always leave the XMP Profile enabled and manually down clock DRAM Frequency to the desired / supported value. From this point you can choose to trial and error test lower values, or leave as is.

CAS Latency is the main focus, find the lowest stable value, then fine tune others. It may be useful to look at some lower frequency G.Skill memory kits to get an idea of the timing characteristics.