Again, an RTX 4090 only suffers a 2% performance loss when used on a PCIe 3.0 x16 slot.
Maybe I miss read the article, but I thought that it was the PCIe subsystem itself that was over heating and not the device itself that was overheating?
The main hot spots are going to be under the CPU, the chipset, and the VRM. Maybe a warm spot under the RAM, SSD, and GPU.
I don’t know which drives temperature up more: the number of lames or the amount of data transmitted by each one. As the SAMSUNG SSD 990 EVO shows, PCIe 5.0 can run cool, and their product happens to use a mere two lanes in PCIe 5.0 mode.
It’s speculation, but perhaps operating fewer lanes at higher speeds actually results in less heat being generated, so long as the unused lanes remain unused (i.e., no connecting 4 PCIe 6.0 lanes to 4 SSDs). We’ll know if the trade-off is real in a few years.
You mean like U.2?
Isn't M.2 is limited to just 12 W? That's really not very much, especially when you consider they only use that much under heavy loads. A hard drive can spike above that, not to mention some of the U.2 drives out there which I've seen specified at a max dissipation of over 20 W.
If you copy around VM images and snapshots or do lots of video editing, then a you can actually see the difference in sequential speed. For more basic stuff, even a decent SATA SSD is still fine.
An yet in your signature you have a x3d CPU that, wait for it, runs at lower clocks to keep temps in check, clearly we don't have the technology yet to handle cache like that but it didn't keep you from buying that CPU.
In some use cases PAM4 encoding allows reduced clock speeds because it transmits more data per clock cycle. Like I know in Nvidia Ampere GPUs that used gddr6x memory, they actually ran at lower clock speeds but used PAM4 encoding to increase data transmitted per cycle by 2x to end up at higher data rates than standard gddr6.
You’re right. It’s 100% the PCIe controllers that heat up rather than the traces themselves. Also a lot of the heat is coming from device controllers running at higher speeds to match the PCIe controllers. If one actually reads the article it’s pretty clear that’s the sort of thing they’re talking about.
Still better than AMD that is slowly turning into an explosives company in their attempt to keep up.
In the case of PCIe 6.0, it runs at the same clockspeed as PCIe 5.0, but has the added overhead of PAM4, FEC, and flits. Therefore, the only reason PCIe 6.0 would burn more power is due to "encoding improvements"!
Well...
Servers already are about as dense as can be, and I think PCIe specs stipulate what distances they need to support. Anyway, if you're a SSD or CPU maker, then it's somewhat out of your hands how closely together a server manufacturer decides to place them, as long as it's within spec.
Yeah, there's already a PCIe working group that's looking at optical. At this point, we know PCIe 7.0 will still support copper, but I haven't heard anything about 8.0.
Sooo.... UCIe?
A broken CPU is a broken CPU. Intel CPUs are literally killing themselves due to too much power and heat, as Intel deliberately allowed motherboard vendors to use an uncapped power limit and just let the CPU thermal throttle.
I'm not saying it's going to be needed now, or next year, or the year after, but it's the next generation of a standard that is widely, widely used at the consumer level, and there's also been a trend towards running smaller links at higher speeds rather than increasing the number of lanes that CPUs make available and that devices can utilize. One product totally saturating a 5.0 x16 link is unlikely, but if the link is split x8/x4/x4 and is dropping to an older version and also cutting the link width shared among those three devcies to x8, that might be something to watch how well future devices handle. Not an immediate concern, but a trend to possibly keep an eye on.
I didn't think PCIe 5.0 would reach consumers so early. Since it did, I wouldn't be too surprised if 6.0 also gets here. Relatively speaking, I'd guess 6.0 doesn't necessarily use that much more power, but the issue for using it in consumer products might be the additional PCB costs (more layers, retimers, materials, etc.) needed to support the higher SNR requirements.
I think we have.
Consider that PCIe 6.0 runs at the same frequency as PCIe 5.0 and the main source of additional power is its encoding. Unlike I/O, the logic implementing that can potentially improve in energy efficiency with more advanced process nodes. It should absolutely be an efficiency win to replace a PCIe 5.0 link with a PCIe 6.0 link that's half the width.
I'm not sure what that's based on, but let's wait and see how much cost it adds to server boards.
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