News Intel 3 '3nm-class' process technology is in high-volume production: Intel

[Admin]

Intel details its 3nm-class process technology: 18% higher performance than 4nm-class, 1.2V support.

Intel 3 '3nm-class' process technology is in high-volume production: Intel : Read more

 

[The Historical Fidelity]

Well it’s official, now Intel’s nm designation is copium. Intel 3 is classified as 5nm according to IEEE specifications with 50nm gate pitch and 30nm interconnect pitch. TSMC N3 actually beats IEEE specifications for 3nm at 48nm gate pitch and 23nm interconnect pitch.

 

[thestryker]

Well it’s official, now Intel’s nm designation is copium. Intel 3 is classified as 5nm according to IEEE specifications with 50nm gate pitch and 30nm interconnect pitch. TSMC N3 actually beats IEEE specifications for 3nm at 48nm gate pitch and 23nm interconnect pitch.

I'm sure the IEEE would be surprised to know they set industry specifications for process nodes good thing you're here to let everyone know.

 

[The Historical Fidelity]

I'm sure the IEEE would be surprised to know they set industry specifications for process nodes good thing you're here to let everyone know.

I’m pretty sure IEEE knows about their own “Semiconductor Standards Association” and their yearly “International Roadmap for Devices and Systems” reports.

 

[NinoPino]

Well it’s official, now Intel’s nm designation is copium. Intel 3 is classified as 5nm according to IEEE specifications with 50nm gate pitch and 30nm interconnect pitch. TSMC N3 actually beats IEEE specifications for 3nm at 48nm gate pitch and 23nm interconnect pitch.

Sssssh, don't say it to Intel investors. 😀

 

[thestryker]

I’m pretty sure IEEE knows about their own “Semiconductor Standards Association” and their yearly “International Roadmap for Devices and Systems” reports.

Which doesn't set "measurement" standards for the industry and is based on what the industry is doing and thus shifts categorization accordingly. If you look at earlier reports what you're claiming defines 3nm was 5nm as IRDS is based on what is happening not setting standards. GMT is no more a "standard" than LMC is they're just measurement techniques.

 

[bit_user]

Intel on Wednesday said that its 3nm-class process technology called Intel 3 has entered high volume production at two sites as well as provided some additional details about the new production node.

Seems like a foregone conclusion, given that Sierra Forest launched and that's based on Intel 3. So is Granite Rapids, which they say is on track.

I'm not saying the extra details aren't nice for some, but if you were paying attention this should come as no surprise.

 

[Blastomonas]

Thought they were still working on 10nm..

 

[ToBeGood]

Sssssh, don't say it to Intel investors. 😀

Hi TSMC fanboy,

Sssssh, just want to say to you quietly that N3E is N5++ is a 5nm class device, N3B != N3E
Sssssh, Intel Sierra Forest is now out as well, just same time frame is Apple M4,
Sssssh, Intel catch up with TSMC.

Sssssh, do let the TSMC shareholder knows.

 

[bit_user]

Sssssh, Intel catch up with TSMC.

What's funny about this claim is that Lunar Lake supposedly used TSMC N3(B?) because it was the best-performing node available to the designers, at the time. So, what do you suppose it says that the designers chose it over Intel 3?

 

[thestryker]

What's funny about this claim is that Lunar Lake supposedly used TSMC N3(B?) because it was the best-performing node available to the designers, at the time. So, what do you suppose it says that the designers chose it over Intel 3?

To be fair to Intel here the chances of Intel 3 being available for LNL is approximately zero due to capacity (Intel 4 and 3 use the same equipment and fabs). That being said I'd be surprised if Intel 3 would have been as good for it as N3B (the high density might be for high efficiency mobile, but not enough details to know one way or the other).

 

[TerryLaze]

What's funny about this claim is that Lunar Lake supposedly used TSMC N3(B?) because it was the best-performing node available to the designers, at the time. So, what do you suppose it says that the designers chose it over Intel 3?

I guess it says that designers can't tell the future?!
'At the time' was how many years ago? I don't keep tabs on this sort of thing, was intel 3 done by then?
Also if it is supposedly, as you claim, then why are you even bringing it up? Make sure it is first.

 

[ToBeGood]

To be fair to Intel here the chances of Intel 3 being available for LNL is approximately zero due to capacity (Intel 4 and 3 use the same equipment and fabs). That being said I'd be surprised if Intel 3 would have been as good for it as N3B (the high density might be for high efficiency mobile, but not enough details to know one way or the other).

Although it is just only a powerpoint at this moment, but the paper on PPA the graph just plot Intel 3 @ 0.65V can clock to Apple M4 i.e. 4.4 GHz, meaning that we should see Xeon 6 (Rapid one), should clock at this speed.

So What Intel indirectly saying is that Intel 3 can clock at least the same level as N3E.

@bit_user Capacity is an issue for Intel, look LnL and TSMC was in the plan from long long time, back when Bob Swarm is the CEO, no matter what, it should be realised that it is so difficult to switch from node A to node B, is easy, if that is that easy, as Apple M4 is already on TSMC N3E, so why LnL is N3B ?? we can understand that the same level of discount to Apple i.e. buying only the good chip will happen @ LnL, that is TSMC cost not Apple nor Intel. Intel will not redesign anything, TSMC will have to pay for this, if you have this good discount from TSMC are you as Intel just forgoes ???

 

[NinoPino]

Hi TSMC fanboy,

Is it your best argumentation ?

Sssssh, just want to say to you quietly that N3E is N5++ is a 5nm class device, N3B != N3E
Sssssh, Intel Sierra Forest is now out as well, just same time frame is Apple M4,
Sssssh, Intel catch up with TSMC.

I'll wait benchmarks to judge, and I sincerely hope Intel do well than last iterations.

Sssssh, do let the TSMC shareholder knows.

No need, tell them, I suppose nobody scared. 😀

 

[NinoPino]

Although it is just only a powerpoint at this moment, but the paper on PPA the graph just plot Intel 3 @ 0.65V can clock to Apple M4 i.e. 4.4 GHz, meaning that we should see Xeon 6 (Rapid one), should clock at this speed.

Clock speed does not depend only on the silicon but also on the logic design, your comparision vs M4 and statement on clock speed is simplistic.

So What Intel indirectly saying is that Intel 3 can clock at least the same level as N3E.

Intel already clock high.

@bit_user Capacity is an issue for Intel, look LnL and TSMC was in the plan from long long time, back when Bob Swarm is the CEO,

To me result that was Gelsinger to choose this way.

no matter what, it should be realised that it is so difficult to switch from node A to node B, is easy, if that is that easy, as Apple M4 is already on TSMC N3E, so why LnL is N3B ?? we can understand that the same level of discount to Apple i.e. buying only the good chip will happen @ LnL, that is TSMC cost not Apple nor Intel. Intel will not redesign anything, TSMC will have to pay for this, if you have this good discount from TSMC are you as Intel just forgoes ???

Cannot get the point.

 

[The Historical Fidelity]

Which doesn't set "measurement" standards for the industry and is based on what the industry is doing and thus shifts categorization accordingly. If you look at earlier reports what you're claiming defines 3nm was 5nm as IRDS is based on what is happening not setting standards. GMT is no more a "standard" than LMC is they're just measurement techniques.

Okay, regardless of your opinion on the matter, my point remains the same, Intel 3/4 is equivalent in size to TSMC N4/5 (50nm gate pitch & 30nm interconnect pitch vs 51nm gate pitch & 28nm interconnect pitch respectively) with TSMC N4/5 beating Intel 3/4 in transistor density.

 

[edzieba]

Well it’s official, now Intel’s nm designation is copium.

So have everyone's process designations since ~28nm when the gate oxide thickness limit was reached. Where have you been the last decade and a half? The only change Intel have made recently has been stopping with the plus-plus-plus-plus suffixes and joining in with the rest of the industry arbitrary number-goes-down games.

 

[ToBeGood]

Okay, regardless of your opinion on the matter, my point remains the same, Intel 3/4 is equivalent in size to TSMC N4/5 (50nm gate pitch & 30nm interconnect pitch vs 51nm gate pitch & 28nm interconnect pitch respectively) with TSMC N4/5 beating Intel 3/4 in transistor density.

Hi TSMC Fanboys @The Historical Fidelity @NinoPino

Regardless these are fact, intel prepared (a possible biased) paper vs TSMC ~x% which one I need to say, there are a lot of professional website out there that mentioned that TSMC N3E = N5 SRAM in um2 i.e. 0.021um2 (HDC) and 0.025um2 (HCC) then look at the powerpoint and google search what is the number from wiki is Intel 4 SRAM in um2 is 0.025um2 (HP) and Intel 3 in um2 (educated guess using the 210:240 ration on the slide) is 0.021um2, then Intel 3 is so identical in size. The pitch is very similar actually within the margin of manufacturing errors, 2nm (4%), The reference is the below webpage.

https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-even

Meteor Lake Die Shot and Architecture Analysis – Why Is Intel 4 Only A 40% Area Reduction Versus Intel 7?

Die shot analysis shows 40% area reduction on identical structures from Intel 7 to Intel 4. Analysis on Redwood Cove and Crestmont architecture, Foveros Omni, Intel's use of TSMC N3 in the GPU, and SOC/IO chiplets

www.semianalysis.com

Then the rest of the density is in unknown area, as I am not sure using TSMC ration (RAM, Logic, Analog) ration of chip and the additional scaling still taking place except SRAM from TSMC N5 to N3E, so using the same ration, will Intel 3 match. But purely on SRAM size, Intel 3 = TSMC N3E.

Then on power, the slide also discussed, @0.65V intel mentioned can clock to around 4.4GHz, very close to what Apple M4 is on TSMC N3E.

TSMC Shareholders needed to be afraid, because TSMC lead is gone, if rumors is true that there is some Arrow Lake parts coming out from 20A this year (some even suggest Oct24), that meant that within weeks if not now, Intel 20A is started Risk Production somewhere, and TSMC is no where to be seen. No because the lead is so important but the velocity of the catch up, the fail N3B node, the promised N2P (BSPD) sorry this TSMC management make too many unforce errors, just like Bob Swam @ Intel, and remember Intel share price is also going very well helped by COVID, but then I knew that they are falling from the grace, very similar to what TSMC current is.

TSMC NEVER delay, they just change names as it please i.e. TSMC N3B a fail node then rename 5nm Class in N3E Oh I am great I am 3nm class, LOL, cheating yourself. Oh I can't do BSPD in N2P, so now add additional node name PowerPoint it to be "Super"rail name it A16 Now I win AGAIN, the whole fan club is now saying TSMC now is A16 way better then 20/18A because you are 18 and I am 16 (TSMC Fan club is a Girl of course Sweet 16 is better then 18)

And with their Intel 3 pipeline, I think Intel Arc will likely to be made with Intel 3-PT or Intel 18A. Then it will be the base die then Intel move back to 100% manufacturing, if and if Intel Arc do capture 25% of GPU market, with existing 70-80% CPU market, chip set, Microsoft, DoD contacts, Tower Semi, etc etc etc, I think in the mid term IFS can stand its ground and a very profitable division,

Intel don't needed care about AI (as GPU designer), they just care will they Fab the next AI gen chip, the answer is Yes, Not TSMC, is Intel, who owned / control ChatGPT, oh yes it open source but everyone thinks that Android is kinda of owned by Google, then ChatGPT is by Microsoft, and where Microsoft going to make it's AI chip and make sure OpenAI will support it, it is Intel will FAB next gen AI chip, Not nVidia, and TSMC, sorry the TSMC-nVidia alliance look very risky to me, nowdays with LLVM nVidia, Intel, AMD is not that important for OpenAI.

 

[The Historical Fidelity]

Hi TSMC Fanboys @The Historical Fidelity @NinoPino

Regardless these are fact, intel prepared (a possible biased) paper vs TSMC ~x% which one I need to say, there are a lot of professional website out there that mentioned that TSMC N3E = N5 SRAM in um2 i.e. 0.021um2 (HDC) and 0.025um2 (HCC) then look at the powerpoint and google search what is the number from wiki is Intel 4 SRAM in um2 is 0.025um2 (HP) and Intel 3 in um2 (educated guess using the 210:240 ration on the slide) is 0.021um2, then Intel 3 is so identical in size. The pitch is very similar actually within the margin of manufacturing errors, 2nm (4%), The reference is the below webpage.

https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-even

Meteor Lake Die Shot and Architecture Analysis – Why Is Intel 4 Only A 40% Area Reduction Versus Intel 7?

Die shot analysis shows 40% area reduction on identical structures from Intel 7 to Intel 4. Analysis on Redwood Cove and Crestmont architecture, Foveros Omni, Intel's use of TSMC N3 in the GPU, and SOC/IO chiplets

www.semianalysis.com

Then the rest of the density is in unknown area, as I am not sure using TSMC ration (RAM, Logic, Analog) ration of chip and the additional scaling still taking place except SRAM from TSMC N5 to N3E, so using the same ration, will Intel 3 match. But purely on SRAM size, Intel 3 = TSMC N3E.

Then on power, the slide also discussed, @0.65V intel mentioned can clock to around 4.4GHz, very close to what Apple M4 is on TSMC N3E.

TSMC Shareholders needed to be afraid, because TSMC lead is gone, if rumors is true that there is some Arrow Lake parts coming out from 20A this year (some even suggest Oct24), that meant that within weeks if not now, Intel 20A is started Risk Production somewhere, and TSMC is no where to be seen. No because the lead is so important but the velocity of the catch up, the fail N3B node, the promised N2P (BSPD) sorry this TSMC management make too many unforce errors, just like Bob Swam @ Intel, and remember Intel share price is also going very well helped by COVID, but then I knew that they are falling from the grace, very similar to what TSMC current is.

TSMC NEVER delay, they just change names as it please i.e. TSMC N3B a fail node then rename 5nm Class in N3E Oh I am great I am 3nm class, LOL, cheating yourself. Oh I can't do BSPD in N2P, so now add additional node name PowerPoint it to be "Super"rail name it A16 Now I win AGAIN, the whole fan club is now saying TSMC now is A16 way better then 20/18A because you are 18 and I am 16 (TSMC Fan club is a Girl of course Sweet 16 is better then 18)

And with their Intel 3 pipeline, I think Intel Arc will likely to be made with Intel 3-PT or Intel 18A. Then it will be the base die then Intel move back to 100% manufacturing, if and if Intel Arc do capture 25% of GPU market, with existing 70-80% CPU market, chip set, Microsoft, DoD contacts, Tower Semi, etc etc etc, I think in the mid term IFS can stand its ground and a very profitable division,

Intel don't needed care about AI (as GPU designer), they just care will they Fab the next AI gen chip, the answer is Yes, Not TSMC, is Intel, who owned / control ChatGPT, oh yes it open source but everyone thinks that Android is kinda of owned by Google, then ChatGPT is by Microsoft, and where Microsoft going to make it's AI chip and make sure OpenAI will support it, it is Intel will FAB next gen AI chip, Not nVidia, and TSMC, sorry the TSMC-nVidia alliance look very risky to me, nowdays with LLVM nVidia, Intel, AMD is not that important for OpenAI.

Okay Intel fanboy, a lot of assumptions and guesses you are pulling out of the nether. Processes are judged based on gate/interconnect pitch and transistor density, and based on those numbers, Intel 3/4 is equivalent to TSMC n4/5. My point remains that Intel was a crybaby when TSMC called their 10nm process N7 while Intel called theirs 10nm. Now they are doing the same thing to TSMC. Hypocrites all around. Whine and complain until you can do the same thing to them.

 

[TheSecondPower]

"Intel has always positioned its Intel 3 fabrication process...Intel promises that the new node will enable 18% higher performance at the same power and transistor density compared to Intel 3." I'm guessing that was meant to compare Intel 4 to 3 and not 3 to 3.

 

[The Historical Fidelity]

So have everyone's process designations since ~28nm when the gate oxide thickness limit was reached. Where have you been the last decade and a half? The only change Intel have made recently has been stopping with the plus-plus-plus-plus suffixes and joining in with the rest of the industry arbitrary number-goes-down games.

Thank you for lecturing me on something everyone has known about for a decade now. Appreciate it

 

[The Historical Fidelity]

"Intel has always positioned its Intel 3 fabrication process...Intel promises that the new node will enable 18% higher performance at the same power and transistor density compared to Intel 3." I'm guessing that was meant to compare Intel 4 to 3 and not 3 to 3.

I don’t disagree with you, but Intel’s entire reason for renaming Intel 10nm to Intel 7 and 7nm to Intel 4 was to bridge the gap between Intel’s designation scheme with TSMC’s optimistic naming scheme. Yet now Intel is being optimistic. Just pointing out the hypocrisy lol, and everyone is coming to their favorite “money takers” defense. The Copium is strong with some of these commenters.

But I believe you are correct!

 

[TerryLaze]

Well it’s official, now Intel’s nm designation is copium. Intel 3 is classified as 5nm according to IEEE specifications with 50nm gate pitch and 30nm interconnect pitch. TSMC N3 actually beats IEEE specifications for 3nm at 48nm gate pitch and 23nm interconnect pitch.

Okay Intel fanboy, a lot of assumptions and guesses you are pulling out of the nether. Processes are judged based on gate/interconnect pitch and transistor density, and based on those numbers, Intel 3/4 is equivalent to TSMC n4/5.

So how does one translate 48nm and 23nm into 4/5nm?
Why are you saying that processes are judged by their pitch and density, when it's all just fantasy numbers?

TSMCs 4/5nm is a fantasy name and so is INTELs 4nm, the nm numbers just represent the increase in performance per size without having any justification at all for it, they just say we have so and so much improvement we are gonna call it a new node now.

My point remains that Intel was a crybaby when TSMC called their 10nm process N7 while Intel called theirs 10nm. Now they are doing the same thing to TSMC. Hypocrites all around. Whine and complain until you can do the same thing to them.

Well they cried about it, nobody changed anything so they joined them instead and instead of crying now they are doing the same as the others.

 

[The Historical Fidelity]

“

Well they cried about it, nobody changed anything so they joined them instead and instead of crying now they are doing the same as the others.

My point exactly…I find the hypocrisy hilarious.

 

[bit_user]

To be fair to Intel here the chances of Intel 3 being available for LNL is approximately zero due to capacity (Intel 4 and 3 use the same equipment and fabs).

How do you know that? It's just a tile with 4P + 4E cores - not the entire SoC.

I guess it says that designers can't tell the future?!

At some point in process node development, test wafers are produced to inform and validate development of the cell library. The resulting information is fed into EDA tools so they know the timing rules and other limitations. By this point, you'd know the key features and properties of a process node and it's probably this information the designers compared between Intel and TSMC processes that informed their decision.

'At the time' was how many years ago? I don't keep tabs on this sort of thing, was intel 3 done by then?

I'm just repeating what Intel said. Try asking them.