News Intel 3 '3nm-class' process technology is in high-volume production: Intel

[bit_user]

The only change Intel have made recently has been stopping with the plus-plus-plus-plus suffixes and joining in with the rest of the industry arbitrary number-goes-down games.

Well, there's also the alphabetic suffixes, now.

 

[TerryLaze]

“

My point exactly…I find the hypocrisy hilarious.

Hypocrisy would be if they did the same thing before/while crying about others doing it.
Intel doing it AFTER having cried about it makes it something else and not hypocrisy.

 

[The Historical Fidelity]

Hypocrisy would be if they did the same thing before/while crying about others doing it.
Intel doing it AFTER having cried about it makes it something else and not hypocrisy.

Right…it’s hypocrisy with extra steps lol

 

[TerryLaze]

Right…it’s hypocrisy with extra steps lol

If you have to use extra steps to get to hypocrisy then it was something else before the extra steps.

 

[thestryker]

Okay, regardless of your opinion on the matter, my point remains the same, Intel 3/4 is equivalent in size to TSMC N4/5 (50nm gate pitch & 30nm interconnect pitch vs 51nm gate pitch & 28nm interconnect pitch respectively)

Yes the size is approximately the same.

with TSMC N4/5 beating Intel 3/4 in transistor density.

Which transistor density are you looking at for TSMC? Intel 4 was high power only which tends to have worse density. Every measurement of the N5 HP cells I've seen indicates they're quite a bit worse in density than Intel 4.

As for Intel 3 it is actually a full node and I don't believe anyone has enough information to work out correct density yet. If you have any information regarding it by all means share.

 

[thestryker]

How do you know that? It's just a tile with 4P + 4E cores - not the entire SoC.

What exactly does it be just a compute tile matter? Intel was never going to prioritize a client product over enterprise when it comes to the new node. The broad time range rollout for GNR/SRF should make it obvious that there isn't enough capacity.

 

[The Historical Fidelity]

Yes the size is approximately the same.

Which transistor density are you looking at for TSMC? Intel 4 was high power only which tends to have worse density. Every measurement of the N5 HP cells I've seen indicates they're quite a bit worse in density than Intel 4.

As for Intel 3 it is actually a full node and I don't believe anyone has enough information to work out correct density yet. If you have any information regarding it by all means share.

The article lists the specs for Intel 3 compared to Intel 4 and they are exactly the same: 50nm gate pitch and 30nm interconnect pitch with the same 240nm height library however they added a 210nm height library for low power applications. And according to Intel themselves, Intel 3 offers up to 10% higher density [1] compared to Intel 4 which has a density of 123.4 MTr/mm^2 [2] so Intel 3 has maximum 135.74 MTr/mm^2 density using the low power library based on Intel’s own claims. TSMC N5 density is 138.2 [3]. TSMC N4 is 143.7 [4]., TSMC N3/E/P-X is 197, 215.6, & 224.2 respectively [4,5,6].

1.https://community.intel.com/t5/Blogs/Intel-Foundry/Intel-Foundry/Intel-Delivers-Leading-Edge-Foundry-Node-with-Intel-3-Technology/post/1607454

2. https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/

3. https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

4.https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/

5.https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/

6.https://www.anandtech.com/print/18833/tsmc-details-3nm-evolution-n3e-on-schedule-n3p-n3x-deliver-five-percent-gains

 

[ToBeGood]

Okay Intel fanboy, a lot of assumptions and guesses you are pulling out of the nether. Processes are judged based on gate/interconnect pitch and transistor density, and based on those numbers, Intel 3/4 is equivalent to TSMC n4/5. My point remains that Intel was a crybaby when TSMC called their 10nm process N7 while Intel called theirs 10nm. Now they are doing the same thing to TSMC. Hypocrites all around. Whine and complain until you can do the same thing to them.

Please can I have the same data from TSMC, the ratio and rational is all come from TSMC PowerPoint, the fanboy out there living in its world always used Xnm+++++ to intel, even long after Intel 20A naming, we are not crying babies, I just want to say, the same has to happen, There is no TSMC A16 from today onward TSMC A16 = TSMC N2P+++ and TSMC N2P = TSMC N2++ ha ha

At some point in process node development, test wafers are produced to inform and validate development of the cell library. The resulting information is fed into EDA tools so they know the timing rules and other limitations. By this point, you'd know the key features and properties of a process node and it's probably this information the designers compared between Intel and TSMC processes that informed their decision.

EDA tools can "help" to transform design from node A to node B, a (team of) person(s) needed to go to each area to confirm the automated transformed design, it is not like you send a file of TSMC N3B to EDA then out file is TSMC N3E. You know nothing.

'At the time' was how many years ago? I don't keep tabs on this sort of thing, was intel 3 done by then?

Now days everything is online

Intel outsourcing – US chip stalwart looks to Asian firms for help

One of the world's largest semiconductor firms, Intel is being forced to break with half a century of in-house production.

techwireasia.com

So it was public known 4 years ago.

 

[thestryker]

The article lists the specs for Intel 3 compared to Intel 4 and they are exactly the same: 50nm gate pitch and 30nm interconnect pitch with the same 240nm height library however they added a 210nm height library for low power applications. And according to Intel themselves, Intel 3 offers up to 10% higher density [1] compared to Intel 4 which has a density of 123.4 MTr/mm^2 [2] so Intel 3 has maximum 135.74 MTr/mm^2 density using the low power library based on Intel’s own claims. TSMC N5 density is 138.2 [3]. TSMC N4 is 143.7 [4]., TSMC N3/E/P-X is 197, 215.6, & 224.2 respectively [4,5,6].

So what you're saying is that you couldn't be bothered to read your own source articles and instead opted to spread misinformation based on incomplete information.

From the second link you provided:

To that end, we estimate Intel 4 at 123.4 MTr/mm², 2.04x from 60.5 MTr/mm² in Intel 7. Our data for TSMC N5 is very much incomplete but our rough estimates based on known pitches put their HP library at 94.85 MTr/mm². Based on most of the recent publically available foundry data, Intel 4 HP cells appear denser than TSMC N5 HP and are likely closer to or better than TSMC N3 HP cells and denser than Samsung’s 3GAE. Given the turmoil 10nm had on the company over the last three years, coming out of it with that kind of numbers is quite surprising. It also strongly suggests Intel 3 can match and surpass upcoming 3nm-class foundry offerings.

https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/

From the third link you provided:

H280g57 gives a logic density of 92.3 MTr/mm² for 3-fin N5. Coincidentally, this just happens to be around the average chip density of NVIDIA’s H100 and Alibaba Yitian 710.

Now we observe that 3-fin N5 has a lower density than the 3-fin Intel 4 process. Intel 4’s sole 3-fin library (H240g50) has a density of 122.8 MTr/mm².

https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

 

[The Historical Fidelity]

So what you're saying is that you couldn't be bothered to read your own source articles and instead opted to spread misinformation based on incomplete information.

From the second link you provided:

https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/

From the third link you provided:

https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

Jeez, read all the articles entirely. Do I have to baby you? You are the one spreading disinformation because you clearly have not read the articles and are claiming BS because you are claiming the Nvidia H100’s actual transistor density using a custom process tailored to Nvidia’s use case (IE: TSMC 4N) means TSMC N5 is the same density. Also, second source directly states they are completely guessing TSMC’s density based on incomplete information. Then the fourth article by the same author states 138.2 with complete information and even published a graph stating actual N5 = 138.2, actual N4 = 143.7, estimated N3 = 215.6.
https://fuse.wikichip.org/wp-content/uploads/2022/12/tsmc-5nm-3nm-density-q1-2023.png

 

[thestryker]

Jeez, read all the articles entirely. Do I have to baby you? You are the one spreading disinformation because you clearly have not read the articles and are claiming BS because you are claiming the Nvidia H100’s actual transistor density using a custom process tailored to Nvidia’s use case (IE: TSMC 4N) means TSMC N5 is the same density. Also, second source directly states they are completely guessing TSMC’s density based on incomplete information. Then the fourth article by the same author states 138.2 with complete information and even published a graph stating actual N5 = 138.2, actual N4 = 143.7, estimated N3 = 215.6.
https://fuse.wikichip.org/wp-content/uploads/2022/12/tsmc-5nm-3nm-density-q1-2023.png

I'm capable of both reading and understanding, but you obviously aren't. You do not seem to grasp that node density isn't static and high performance always lowers density. That graph is for high density and the article even says so:

At a 48-nanometer CPP, the 143 nm HD cells give a transistor density of around 215.6 MTr/mm2.

Talking about HP N3:

At a 48-nanometer CPP, the 169 nm HP cells work out to around 182.5 MTr/mm2. The 3-nanometers high-performance cells (H221) with a 54-nanometer CPP produces a transistor density of around 124.02 MTr/mm2.

From this article: https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/
With this graph: https://fuse.wikichip.org/wp-content/uploads/2022/12/hp-density-14nm-5nm.png

 

[The Historical Fidelity]

I'm capable of both reading and understanding, but you obviously aren't. You do not seem to grasp that node density isn't static and high performance always lowers density. That graph is for high density and the article even says so:


Talking about HP N3:

From this article: https://fuse.wikichip.org/news/7375/tsmc-n3-and-challenges-ahead/
With this graph: https://fuse.wikichip.org/wp-content/uploads/2022/12/hp-density-14nm-5nm.png

Again you are presenting an educated guess as actual fact. 124.02 is clearly marked as an estimate for TSMC N3 vs actual 123.4 for Intel 4. You are just digging yourself into a bigger hole….

 

[thestryker]

Again you are presenting an educated guess as actual fact. 124.02 is clearly marked as an estimate for TSMC N3 vs actual 123.4 for Intel 4. You are just digging yourself into a bigger hole….

No you're the one who is claiming high density and high performance are the same thing. They are not the same thing and you refuse to admit that fact. I'm not going to keep going in circles with you as you're conveniently ignoring that which doesn't fit your stance. I thought you were actually worth discussing with, but unfortunately I overestimated your capacity to understand reality.

 

[The Historical Fidelity]

No you're the one who is claiming high density and high performance are the same thing. They are not the same thing and you refuse to admit that fact. I'm not going to keep going in circles with you as you're conveniently ignoring that which doesn't fit your stance. I thought you were actually worth discussing with, but unfortunately I overestimated your capacity to understand reality.

Ad hominem attacks really don’t look good on you.
I have never specified I was talking about HP over HD. You put those words in my mouth. Density to density….TSMC wins. Look back at my original post that you began TLDR refuting me over “The article lists the specs for Intel 3 compared to Intel 4 and they are exactly the same: 50nm gate pitch and 30nm interconnect pitch with the same 240nm height library however they added a 210nm height library for low power applications. And according to Intel themselves, Intel 3 offers up to 10% higher density [1] compared to Intel 4 which has a density of 123.4 MTr/mm^2 [2] so Intel 3 has maximum 135.74 MTr/mm^2 density using the low power library based on Intel’s own claims. TSMC N5 density is 138.2 [3]. TSMC N4 is 143.7 [4]., TSMC N3/E/P-X is 197, 215.6, & 224.2 respectively [4,5,6].”

Please tell me where your brain began assuming I was talking about HP libraries? Because I’m specifically comparing Intel 3’s HD 210nm height library (IE Intel’s most dense version of Intel 3) vs the published TSMC N5/N4 densities.

Face it, you’re wrong, and you have been changing the focus and using estimations as fact to try and eke out a disingenuous win at all costs. I’ve had enough of your antagonistic armchair toxicity.

 

[thestryker]

Ad hominem attacks really don’t look good on you.
I have never specified I was talking about HP over HD. You put those words in my mouth. Density to density….TSMC wins. Look back at my original post that you began TLDR refuting me over “The article lists the specs for Intel 3 compared to Intel 4 and they are exactly the same: 50nm gate pitch and 30nm interconnect pitch with the same 240nm height library however they added a 210nm height library for low power applications. And according to Intel themselves, Intel 3 offers up to 10% higher density [1] compared to Intel 4 which has a density of 123.4 MTr/mm^2 [2] so Intel 3 has maximum 135.74 MTr/mm^2 density using the low power library based on Intel’s own claims. TSMC N5 density is 138.2 [3]. TSMC N4 is 143.7 [4]., TSMC N3/E/P-X is 197, 215.6, & 224.2 respectively [4,5,6].”

Please tell me where your brain began assuming I was talking about HP libraries? Because I’m specifically comparing Intel 3’s HD 210nm height library (IE Intel’s most dense version of Intel 3) vs the published TSMC N5/N4 densities.

Face it, you’re wrong, and you have been changing the focus and using estimations as fact to try and eke out a disingenuous win at all costs. I’ve had enough of your antagonistic armchair toxicity.

One last attempt because you absolutely refuse to accept what's in front of your face. That 138.2 figure is attached to a graph of high density. The graph for high performance is the other one and it shows 92.7 for N5. Intel 4 is only high performance so it could never compare to high density.

How can you possibly not grasp this yet?

 

[The Historical Fidelity]

One last attempt because you absolutely refuse to accept what's in front of your face. That 138.2 figure is attached to a graph of high density. The graph for high performance is the other one and it shows 92.7 for N5. Intel 4 is only high performance so it could never compare to high density.

How can you possibly not grasp this yet?

Friend, you really need to stop putting words in my mouth. Do you have a habit of making up stuff in your head and projecting it onto others? I never stated I was talking about HP and if Intel failed to make an HD library for Intel 4 then that is on them, and suggests that Intel 3’s 210nm HD library size reduction is a de facto HD library for Intel 4 since Intel 3’s HP library is dimensionally identical to Intel 4 at 240nm height and same 50/30 pitch.

Let me break down my argument so there is absolutely no confusion:

Intel 3 not 4, 3….NO 4, 4-1 =3, 3, I’m talking about…..3, THREE, ONE LESS THAN 4, 2+1=3, ONE MORE THAN 2. VS TSMC N5/N4…..THEY HAVE EQUIVALENT DENSITIES. NO Intel 4, minus 1=3, NO HP, ALWAYS TALK ABOUT HD, MOST DENSE INTEL 3, SMALLEST 210nm library less dense than….maintain focus….PUBLISHED TSMC N4/5 figures. N5 HP NOT RELEVANT TO MY ARGUMENT, 92.7= ESTIMATED NUMBER, Intel 4 123.4=PUBLISHED NUMBER. USING BOTH TO COMPARE NODES = FALLACY.

 

[thestryker]

Friend, you really need to stop putting words in my mouth. Do you have a habit of making up stuff in your head and projecting it onto others? I never stated I was talking about HP and if Intel failed to make an HD library for Intel 4 then that is on them, and suggests that Intel 3’s 210nm HD library size reduction is a de facto HD library for Intel 4 since Intel 3’s HP library is dimensionally identical to Intel 4 at 240nm height and same 50/30 pitch.

Let me break down my argument so there is absolutely no confusion:

Intel 3 not 4, 3….NO 4, 4-1 =3, 3, I’m talking about…..3, THREE, ONE LESS THAN 4, 2+1=3, ONE MORE THAN 2. VS TSMC N5/N4…..THEY HAVE EQUIVALENT DENSITIES. NO Intel 4, minus 1=3, NO HP, ALWAYS TALK ABOUT HD, MOST DENSE INTEL 3, SMALLEST 210nm library less dense than….maintain focus….PUBLISHED TSMC N4/5 figures. N5 HP NOT RELEVANT TO MY ARGUMENT, 92.7= ESTIMATED NUMBER, Intel 4 123.4=PUBLISHED NUMBER. USING BOTH TO COMPARE NODES = FALLACY.

So what it comes down to is you think Intel HP should only be compared to TSMC HD got it.

PS: I originally asked about Intel 4 in addition to 3 which is why I keep going back to 4 because we actually know the real numbers there.

 

[The Historical Fidelity]

So what it comes down to is you think Intel HP should only be compared to TSMC HD got it.

PS: I originally asked about Intel 4 in addition to 3 which is why I keep going back to 4 because we actually know the real numbers there.

I’d love to compare TSMC HP to Intel HP if there were actual published TSMC HP figures. But I will not speculate using estimated densities made with incomplete data as it is disingenuous to do so ( as I have been saying over and over again in previous comments). The ONLY reason I used Intel 4 density numbers is because it is 1. known, 2. There is only one version of Intel 4 thus only one density Intel can be using to produce a gen on gen density increase, and 3. Intel themselves stated Intel 3 is “up to 10% more dense than Intel 4”. Since this article published all the pitches, library heights, and CPP for Intel 3 in a comparison of Intel 3&4 side by side, the ONLY difference is the new optional low power (<0.6V) cell library that is 30nm shorter (210 vs 240) than Intel 4’s ONLY cell library, then Intel 3’s densest form is still worse than TSMC N5’s published figure which I agree with you and would hope is the HD N5 for Intel’s sake.

 

[TheSecondPower]

When Intel announced graphics chips built by TSMC, a lot of people considered it proof that Intel's foundries were inferior to TSMC's. But there's a related story which was forgotten. When AMD moved from Piledriver to Steamroller, desktop CPU performance decreased even with an IPC increase. The reason was that AMD and Global Foundries were trying to build "APUs" with better graphics capabilities. ATI's GPUs were built on TSMC's high density nodes and the graphics logic didn't perform as well on Global Foundries' high performance 32nm node. So for Steamroller, Global Foundries used a new 28nm node that was higher density and lower leakage. The graphics performance of the product was much better than the 32nm Piledriver. And power consumption in low power laptops also improved. But maximum clock speed took a huge hit on desktops.

The same problem cropped up again when Intel started building GPUs. Intel's "10nm" nodes—the last of which was named "Intel 7"—allowed Golden Cove to complete quite strongly against AMD Zen 3 built on TSMC N7. But it was too optimized for frequency and not enough for density and leakage, making it inadequate for Arc GPUs.

High density nodes also struggle in low usage moments in laptops, so Alder Lake doesn't do as well with battery life as the competing Ryzen products. Intel wanted to address this in Meteor Lake, but it came to market before Intel had a high-density node. Intel got around this issue by having two CPU cores built into a tile built on TSMC's density-optimized N6 node. And the GPU was built on the density-optimized N5 node.

Intel 3 is the first Intel node to offer high density. It's also the first one that Intel says has major 3rd-party customers. This is the beginning of Intel even having the option to build GPUs or most 3rd-party products.