News Intel and SoftBank collaborate on power-efficient HBM substitute for AI data centers, says report

[Admin]

SoftBank wants to corner the AI chip memory market with a more efficient substitute to HBM.

Intel and SoftBank collaborate on power-efficient HBM substitute for AI data centers, says report : Read more

 

[The Historical Fidelity]

Since HBM is itself a stacked DRAM solution, the only difference with Intel’s offering will the efficiency of routing data and power lines.
So my question is, will this “efficient wiring” be internal to the stack only? So that the package is interchangeable with HBM on physical boards? Does this new offering retain the same timings and variables as HBM to make it compatible with current HBM memory controllers?
There are many factors not mentioned in this article that will have significant effects on whether Intel-Bank’s offering will survive in the market.

 

[Pierce2623]

So they want to give GDDR the same treatment as modern SSDs gave flash memory, where they increase bandwidth by just accessing many more memory banks concurrently ?

 

[wwenze1]

You need somebody to manufacture it tho.

On one hand it feels like business vapor talk

On the other hand Intel has made memory in the past

On the third hand Intel was also saying how good their new GPU idea will be and look how it turned out...

Any cost-saving idea won't work if the end product still end up more expensive or too low margin

 

[usertests]

https://www.tomshardware.com/news/samsung-reveals-ddr5-7200-512gb-ram

Here's a 2021 story about a 512 GB module using TSV stacked dies. It sounds like they want a lower power alternative to TSVs.

If they are stacking dies, it's a stopgap before true 3D DRAM which would be analogous to V-NAND and have amazing density and higher power efficiency than TSV stacked dies (although it could be combined with that). Samsung is pursuing 32 layers in the early 2030s if I remember correctly.

 

[bit_user]

This will also be the first time that Japan aims to become a major memory chip supplier in over 20 years.

You should say DRAM, when that's what you're talking about, since the term "memory" is sometimes also used to include NAND flash. Japan never left the NAND market.

This won’t be the first time that a semiconductor company is experimenting with 3D stacked DRAM.

Need to distinguish between stacking and 3D DRAM. The former involves die stacking and (apart from HBM) has been around since at least DDR4 (found in high-capacity server DIMMs) and LPDDR5 and might or might not come along with any performance benefits.

3D DRAM refers to layering multiple planes of DRAM cells within a single die, as the NAND industry has done for flash memory, since about a decade ago.

 

[bit_user]

I had an idea about how this might work, BTW. What if Intel's idea is to use hybrid bonding to pair dies? If so, maybe they can combine DRAM control circuitry across a pair of dies, which would align neatly with their 2x efficiency figure. You'd still need TSVs as a communication channel through the entire stack, but the electrical load the memory controller would have to drive could potentially be halved.