News Intel Announces Agilex 7 M-Series FPGAs with R-Tile, PCIe 5.0 and CXL 2.0 Support

[Admin]

Intel today announced its Agilex 7 M-Series FPGAs with R-Tile, bringing the performance of PCIe 5.0 and CXL 2.0 support IP blocks from CPUs to FPGAs for increased performance/watt.

Intel Announces Agilex 7 M-Series FPGAs with R-Tile, PCIe 5.0 and CXL 2.0 Support : Read more

 

[JayNor]

Nice article. Can the CXL 2.0 implementation act as a master?

 

[TerryLaze]

Being more specialized hardware, FPGAs can be used to accelerate workloads that aren't CPU-dependent, thus freeing up valuable CPU resources for their specific tasks

If something isn't cpu-dependent then how much CPU resources is it really going to free up?!
FPGAs are there to run stuff that is very CPU-dependent would you try and run them on a normal CPU, you make your own accelerators on the FPGA for those things.

That should bring about significant improvements in power efficiency and data throughput, which are important elements to lower Total Cost of Ownership (TCO) for high-performance installations. But with these choices, there are always trade-offs: Intel is adding yet another fixed-function hardware block onto a product whose desirability lies in it being programmable. Programmable die area is the FPGA buyer's mantra, after all.

Yes, customers want the FPGA for the FPGA, they don't want to have to use up parts of the precious FPGA to implement PCI and CXL and whatever other standard thing that they only need to get data to the FPGA part fast enough.
More fixed function that end users actually need means more FPGA remains free for the actual work end users want to do on it.

But the only real question is why in the world didn't they call it the R-Type tile...