News Intel Core Ultra 200 CPU specs allegedly leaked — Arrow Lake tops out at 24 cores and 5.7 GHz boost clock at 250W

[Admin]

Core Ultra 200 series CPU specifications have been purportedly finalized. Five SKUs will debut on launch day. Core counts remain the same, but clock speeds are dropping compared to Raptor Lake Refresh.

Intel Core Ultra 200 CPU specs allegedly leaked — Arrow Lake tops out at 24 cores and 5.7 GHz boost clock at 250W : Read more

 

[Eximo]

"Unlike the Core i9-14900K, Intel keeps the same core count configuration, featuring a 2:1 ratio for the P and E-cores."

That doesn't make any sense. Both are 8P + 16E configurations. Unless you are talking about hyperthreading for something.

Also wouldn't it be 1:2 P to E cores?

 

[thestryker]

If the performance in gaming can top X3D parts I'll certainly be onboard with one of the top two SKUs. I know there's no such thing as a perfect CPU, but I'd like to have top tier gaming performance to go with top tier MT.

Intel will also take advantage of third-party silicon again, ditching its homebrewed 18A process node for a competing design from TSMC.

A) It would be 20A
B) We actually don't know what the K SKU manufacturing process is for sure because Intel has been extremely lacking in details. It's not impossible that the Compute Tile on the K SKUs is 20A and none of the undoubtedly many forthcoming lower SKUs/mobile parts are.

 

[Jame5]

I must have missed something somewhere along the way. Is this the first CPU design with more L2 cache than L3 cache? I always thought that L3 > L2 > L1 caches are pretty much by design. each level of cache is larger than the previous, but also slower.

 

[joeer77]

This is Intel 1278 gate all around chip. Incorporating backside power deliver and EUV as well. A radical departure from 1276 FinFET. If it's only 18% faster at best I am going to be disappointed.

 

[thestryker]

I must have missed something somewhere along the way. Is this the first CPU design with more L2 cache than L3 cache? I always thought that L3 > L2 > L1 caches are pretty much by design. each level of cache is larger than the previous, but also slower.

There are technically 4 tiers if cache in this architecture, but the main benefit for L3 has been that it's shared among the cores. So while there is more L2 than L3 everything below L3 isn't shared (for the P-cores, I don't remember if Skymont E-cores share L2 for the 4 core clusters like the predecessors).

 

[TheSecondPower]

I don't remember if Skymont E-cores share L2 for the 4 core clusters like the predecessors

The Skymont LPE cores in Lunar Lake do share a 4 MB L2 cache.

 

[TheSecondPower]

I must have missed something somewhere along the way. Is this the first CPU design with more L2 cache than L3 cache? I always thought that L3 > L2 > L1 caches are pretty much by design. each level of cache is larger than the previous, but also slower.

The Snapdragon X Elite has 36 MB of L2 in 12 MB blocks or 3 MB per core, but only 6 MB of L3.
https://www.anandtech.com/show/21445/qualcomm-snapdragon-x-architecture-deep-dive/2

 

[YSCCC]

Don’t looks like it will have significant performance increase from RPL, and will be interesting to see if the similar power budget will cook it also

 

[Amdlova]

They need to call it Pentium D 285k (will be hot and put your house on fire)

 

[ingtar33]

if these are going to be more cpus pulling in 400W of peak power i don't know how anyone would risk buying one after the disaster with 13th and 14th gen cooking themselves.

 

[YSCCC]

if these are going to be more cpus pulling in 400W of peak power i don't know how anyone would risk buying one after the disaster with 13th and 14th gen cooking themselves.

125w pl1 and 250w pl2, same 8p 16 E with all core 5.7 is close enough to 14900k for alarm bell to ring for a lot of ppl

 

[Lucky_SLS]

The ultra 7 chip is an 8+12 core config with 20 threads, not 24.

 

[graham006]

They need to call it Pentium D 285k (will be hot and put your house on fire)

AFAIK no Intel processor has ever burnt down a house.

But AMD has this: https://www.tomshardware.com/news/amd-ryzen-7000x3d-burnout-reports

 

[jokepoke69]

I thought they are on a way smaller node now no, what is this power crap? I was expecting pl2 150W or something not 250W lol.

 

[thestryker]

I thought they are on a way smaller node now no, what is this power crap? I was expecting pl2 150W or something not 250W lol.

Like how AMD moved to a better node and the TDP on the 9950X was totally dropped down from 170W (~230W in the real world) to... oh wait... Then there is always how negative the reaction (whether deserved or not, and I don't really think it was) to the 65W TDP for the 9600X/9700X was that they put in a 105W mode that doesn't require PBO (technically voiding warranty). Both AMD and Intel have decided to blow up power numbers to chase the last bit of performance so even if architecture and process are better the maximum power numbers are going to be dumb.

TDP by itself doesn't really mean a whole lot it's more of what they power usage curve looks like. Intel also left out SMT/HT and raised the boost clocks on the E-cores so they undoubtedly need enough power to keep them at maximum performance for multithreaded. The real question will be how these run efficiency wise on lighter workloads which is where the biggest issue with the current CPUs lie. Maximum and minimum thread counts they're mostly fine (or can be so long as there are power limits) it's the in between they use disproportionate amounts of power.

 

[Bikki]

Intel advertize their Intel 4 node (previously 7nm) has the same density as TSMC 3nm, what is the real reason why they have to abandon their blood line to TSMC?

 

[jp7189]

If the performance in gaming can top X3D parts I'll certainly be onboard with one of the top two SKUs. I know there's no such thing as a perfect CPU, but I'd like to have top tier gaming performance to go with top tier MT.

A) It would be 20A
B) We actually don't know what the K SKU manufacturing process is for sure because Intel has been extremely lacking in details. It's not impossible that the Compute Tile on the K SKUs is 20A and none of the undoubtedly many forthcoming lower SKUs/mobile parts are.

As far as I know, Intel has no plans to fab any silicon for arrow lake. It's all TSMC.

 

[jp7189]

This is Intel 1278 gate all around chip. Incorporating backside power deliver and EUV as well. A radical departure from 1276 FinFET. If it's only 18% faster at best I am going to be disappointed.

Do you have a source for that? Everything I see says gaa and bspdn aren't ready yet. As far as I know they are hoping to use that first in the panther gen

 

[thestryker]

As far as I know, Intel has no plans to fab any silicon for arrow lake. It's all TSMC.

Problem is that Intel hasn't just come out and said either way. I agree it's most likely all TSMC, but with how Intel has been silent with regards to ARL it's impossible to say. If it's accurate the margins this generation of CPUs are going to be atrocious.

Do you have a source for that? Everything I see says gaa and bspdn aren't ready yet. As far as I know they are hoping to use that first in the panther gen

It would have to be 20A for GAAFET and/or BSPDN as neither one is available on any volume nodes currently.

 

[thestryker]

Intel advertize their Intel 4 node (previously 7nm) has the same density as TSMC 3nm, what is the real reason why they have to abandon their blood line to TSMC?

Intel has a limited number of EUV machines and has to use them for Intel 4, 3, 20A and 18A. Intel 4 has only been used in volume for an Ericsson chip and MTL, Intel 3 is a long term node but is currently being used for GNR/SRF, 20A appears to have been abandoned for 18A which is their first leading node opened to third parties. This means the fabs setup to run Intel 4/3 have to keep fulfilling contracted manufacturing on Intel 4 which means that capacity cannot be used for Intel 3.

It isn't illogical to assume Intel ditched 20A to maximize capacity for 18A given the limited fab space available.

 

[joeer77]

Do you have a source for that? Everything I see says gaa and bspdn aren't ready yet. As far as I know they are hoping to use that first in the panther gen

It's in the Intel press releases. TSMC going to run Intel 20A (1278) for them. Intel will crank out 18A node themselves (also 1278). That's been in the news during last week. Both are GAA nodes.

I have a subscription to TechInsights in Canada. I have access to their reports when they dissect chips. Samsung and TSMC capable of GAA chips. Intel still trying to get off the ground.