livebriand
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livebriand
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wow.. the old pentium 4s used 180nm? Yikes, it's amazing to think how much they've shrunk stuff.
[citation][nom]cschuele[/nom]due to physics you can't get past 1-2nm before the gates are so small electrons leak out and dont function correctly. What started 40 years ago is now almost at the limits of physics. Soon there will be no reason to upgrade other added cores and new architecture. Does anyone know the gate sizes on the first processors?[/citation]
depends on what you define as the "first" processor. I would say the intel 4004 was the first. It used 10 micro meters for process size. That would be 10,000 nanometers. But some would call the 8088 the first processor which was a 3 micrometer chip.
depends on what you define as the "first" processor. I would say the intel 4004 was the first. It used 10 micro meters for process size. That would be 10,000 nanometers. But some would call the 8088 the first processor which was a 3 micrometer chip.
[citation][nom]loomis86[/nom]not without carbon nanotubes or nanowires. It will be the end of CMOS on silicon. Maybe they will get to 8 nm with silicon. maybe. The point is, we are getting close to the day when computers are going to have to change drastically if they are going to continue to shrink.[/citation]
I wouldn't be so sure. Every time some says we are getting to the physical limitation of silicon somebody else figures out how to do it. I remember when 32nm chips were hitting the market everyone was concerned, they even went as far as saying Moore's law was coming to an end. Next thing you know someone figured out how to make it happen.
I wouldn't be so sure. Every time some says we are getting to the physical limitation of silicon somebody else figures out how to do it. I remember when 32nm chips were hitting the market everyone was concerned, they even went as far as saying Moore's law was coming to an end. Next thing you know someone figured out how to make it happen.
nottheking
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- Jan 5, 2006
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[citation][nom]lunaticwoda[/nom]Cant wait for 1nm chips[/citation]
*IF* Moore's Law continues to hold indefinitely, we'd see Intel roll out chips with it in 2030. However, Moore's Law will likely finally hit its end before that happens; silicon, for instance, has an atomic spacing of about 0.54 nanometers; this means the current feature size on Ivy Bridge chips will be a mere 41 atoms wide.
Single-atom-width features are essentially impossible here, as that leaves no spacing between them. (fabrication process size refers to the middle-to-middle distance between two parallel gates) That makes 2 atoms the absolute smallest, and that wouldn't work if the material was bound using the same crystalline structure as it is today; carbon nanotubes would be the ultimate boundary there, as they're made using tighter, smaller, and more reliable covalent bonds. Still, given that they require a device that's multiple-atoms-wide, spacing there would likely still not quite reach 1 nm.
[citation][nom]seezur[/nom]I wouldn't be so sure. Every time some says we are getting to the physical limitation of silicon somebody else figures out how to do it. I remember when 32nm chips were hitting the market everyone was concerned, they even went as far as saying Moore's law was coming to an end. Next thing you know someone figured out how to make it happen.[/citation]
There's a difference between "we're not sure how we'll work with materials that'll play nice at this scale" and "we're reaching the point where eventually we'll be at the absolute minimum size before going to zero."
Using CMOS, the main limitation comes from the structure of the silicon. When grown perfectly, the atoms are packed into a cubic crystal lattice structure with about 0.54 nanometers per atom. You can't make something with silicon any smaller than this. In fact, you can't even really reach that with a usable design, since the crystal won't be aligned perfectly to allow for a single, linear path of silicon. Combined with the need for at least perhaps 2 atoms' spacing between features, (again to account for the zig-zag nature of the structure) you're looking at 1.63 nanometers as the minimum spacing. And reaching that, ESPECIALLY by the roughly 2028 deadline in order to maintain Moore's Law, is very unlikely.
Chances are almost certain that we'll be able to replace silicon with carbon nanotubes before we can figure out how to make the "ultimate" silicon process, and hence never use it. And from there, likely if we're to expand, we'll have to make progressively-deeper layered 3D designs, allowing the stacking of not just material layers, but whole designs.
*IF* Moore's Law continues to hold indefinitely, we'd see Intel roll out chips with it in 2030. However, Moore's Law will likely finally hit its end before that happens; silicon, for instance, has an atomic spacing of about 0.54 nanometers; this means the current feature size on Ivy Bridge chips will be a mere 41 atoms wide.
Single-atom-width features are essentially impossible here, as that leaves no spacing between them. (fabrication process size refers to the middle-to-middle distance between two parallel gates) That makes 2 atoms the absolute smallest, and that wouldn't work if the material was bound using the same crystalline structure as it is today; carbon nanotubes would be the ultimate boundary there, as they're made using tighter, smaller, and more reliable covalent bonds. Still, given that they require a device that's multiple-atoms-wide, spacing there would likely still not quite reach 1 nm.
[citation][nom]seezur[/nom]I wouldn't be so sure. Every time some says we are getting to the physical limitation of silicon somebody else figures out how to do it. I remember when 32nm chips were hitting the market everyone was concerned, they even went as far as saying Moore's law was coming to an end. Next thing you know someone figured out how to make it happen.[/citation]
There's a difference between "we're not sure how we'll work with materials that'll play nice at this scale" and "we're reaching the point where eventually we'll be at the absolute minimum size before going to zero."
Using CMOS, the main limitation comes from the structure of the silicon. When grown perfectly, the atoms are packed into a cubic crystal lattice structure with about 0.54 nanometers per atom. You can't make something with silicon any smaller than this. In fact, you can't even really reach that with a usable design, since the crystal won't be aligned perfectly to allow for a single, linear path of silicon. Combined with the need for at least perhaps 2 atoms' spacing between features, (again to account for the zig-zag nature of the structure) you're looking at 1.63 nanometers as the minimum spacing. And reaching that, ESPECIALLY by the roughly 2028 deadline in order to maintain Moore's Law, is very unlikely.
Chances are almost certain that we'll be able to replace silicon with carbon nanotubes before we can figure out how to make the "ultimate" silicon process, and hence never use it. And from there, likely if we're to expand, we'll have to make progressively-deeper layered 3D designs, allowing the stacking of not just material layers, but whole designs.
I was in a lab at IBM and I saw them put 2 billion transistors on a single electron. So in 5 years we are going to see this.
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