News Intel delays key Xeon data center processor amid massive losses — Clearwater Forest pushed back to 1H 2026

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Intel delays key Xeon data center processor amid massive losses — Clearwater Forest pushed back to 1H 2026

Intel delays key Xeon data center processor amid massive losses — Clearwater Forest pushed back to 1H 2026 : Read more

 

[bit_user]

Way worse than their Falcon Shores cancellation. Intel desperately needs Clearwater Forest to help stave off the assault from ARM and AMD. Pretty soon, the RISC-V bros will be joining the ranks of their competition. I wonder if the delay has anything to do with how the CPU chiplets are being stacked on cache dies.

You almost have to laugh at the sad farce that Intel has become, or else you might just cry.

 

[jp7189]

Despite the public wording, I don't think this makes 18A sound healthy. Historically, the high margin datacenter products have stayed in house, and consumer products have been outsourced to TSMC. I'm willing to bet they are designing Panther with hope for 18A, but with an eye on TSMC, and that gives them the confidence to keep Panther on target. Whereas Xeon 7 has no such safety net in the plan.

 

[jheithaus]

Falcon Shores was hopeless. Xe+ x86 + gaudi sounded like a power point presentation completely divorced from technical reality. In view of the consumer success of Xe2, INTC should just scale Xe2 complexity over time and spin out (ipo) Habana. Regardless, INTC should have kept Xeon on schedule. The OT, the rushed steppings, get it done.

 

[thestryker]

Falcon Shores was hopeless. Xe+ x86 + gaudi sounded like a power point presentation completely divorced from technical reality.

They canceled the "XPU" version of Falcon Shores in 2023 this one was just the GPU.

 

[DS426]

It takes a lot of validation before ramping server CPU's, so I guess I'm not surprised. I'm also thinking 18A is being pushed back slightly, which pushed back Panther Lake but not enough to launch after Q4 2025.

Intel can't afford any more delays on their 18A products. To see DCAI rake in almost no earnings and CCG slightly up but Arrow Lake is sizzling out as months of updates haven't really improved its performance... they don't have a lot to ride on thru 2025.

 

[bit_user]

Despite the public wording, I don't think this makes 18A sound healthy.

They confirmed that Panther Lake is using 18A (presumably for the compute tile) and launching in the latter half of this year. That's pretty good.

I'm willing to bet they are designing Panther with hope for 18A, but with an eye on TSMC,

Well, now that their foundry nodes support standard toolchains, it's much easier for them to port designs to one fab or the other. That said, I'd be pretty surprised if they went to TSMC with Panther Lake.

Lunar Lake was targeted at TSMC pretty much from day one. Intel said its designers were given the direction to use the highest-performing node, period. At the time they made that decision, TSMC's node looked better than Intel 3, which was the best alternative Intel would've had available.

Arrow Lake was indeed a surprise, since it was planned to use Intel 20A. However, Intel decided it would be cheaper for them to just use TSMC than do volume product on a special node they're not using for any other products. And it was easy, because they already had the layout for Lion Cove and Skymont, on TSMC N3B, from Lunar Lake. So, I'll bet that rather than port the entire CPU tile from 20A to N3B, they just took the cores from Lunar Lake and redid the rest of Arrow Lake's CPU tile on N3B.

that gives them the confidence to keep Panther on target. Whereas Xeon 7 has no such safety net in the plan.

That's a theory, but given how small the CPU tiles for mobile processors are, their yield tolerance is much higher than big server CPU tiles. Also, they don't need to have ramped production volume as much as they do for server CPUs.

 

[bit_user]

Falcon Shores was hopeless. Xe+ x86 + gaudi

They dropped the x86 tiles a long time ago. AFAIK, Falcon Shores was supposed to just be Xe-based. Where did you hear about Gaudi being in the mix?

In view of the consumer success of Xe2, INTC should just scale Xe2 complexity over time and spin out (ipo) Habana.

I think the opposite. In spite of Nvidia's success, GPUs aren't the optimal architecture for AI. The main advantage of Xe is that it can do both AI and HPC, but I think Intel just needs to give up on HPC, for now.

 

[thestryker]

The main advantage of Xe is that it can do both AI and HPC, but I think Intel just needs to give up on HPC, for now.

I wish I could disagree with you because I find it super compelling from a technology standpoint. I view it similarly to 3D XPoint though: even if something is a good piece of technology that doesn't make it a viable business.

I wonder if the delay has anything to do with how the CPU chiplets are being stacked on cache dies.

This was the first thing I thought of as well since they haven't stacked cache like that on a CPU. The other thing is each base tile has 4 compute tiles on it and I don't recall seeing if the cache design was supposed to be shared among those tiles or if it was separate cache for each. Both would definitely have their own validation complexity but if it was separate for each compute tile that's also extra failure points.

 

[bit_user]

I wish I could disagree with you because I find it super compelling from a technology standpoint.

It pains me to say it, because I've done a bit of OpenCL and SYCL programming on Intel's GPU stack and would quite like to see them continue with this development. If you take HPC off the table, I'm not sure they can justify continuing development on the oneAPI stack.
: (

This was the first thing I thought of as well since they haven't stacked cache like that on a CPU.

They did mention something about packaging, so perhaps it's plausible.

The other thing is each base tile has 4 compute tiles on it and I don't recall seeing if the cache design was supposed to be shared among those tiles or if it was separate cache for each.

I think it's probably a federated L3, like what AMD does. Intel kept using a unified L3 domain for way too long. It worked well for them, but I think they got burnt by carrying it forward into the multi-die era.

Heck, even on the desktop, L3 bandwidth is where Arrow Lake really falls apart. Ryzen 9000 shows AMD's approach is much stronger, here.

Source: https://chipsandcheese.com/p/examining-intels-arrow-lake-at-the
​

 

[jp7189]

They confirmed that Panther Lake is using 18A (presumably for the compute tile) and launching in the latter half of this year. That's pretty good.

They confirmed Arrow on 20A. As I recall it, the public expected Arrow on Intel up until launch day.

I would also say packaging has been a bright spot while node advancement has not. For them to switch it up and blame packaging for the delays this time seems like a ploy to save face on what they consider to be a more important part of the business.

Let me ask this... what is Intel's most advanced healthy node? ..and by healthy I mean profitable to produce low margin consumer chips in high volume. The last one I'm absolutely sure about is Intel 10, but you could make an argument for Intel 7 (renamed to 4), but not in the 60% margin territory that have historically aimed for. It sounds like Intel 3 is still ramping and only for high margin products. Unless they have an absolutely brilliant breakthrough, I wouldn't expect 18a to yield well enough for consumer chips this year. I would love to be wrong, but that's what the indicators are saying to me.

 

[bit_user]

They confirmed Arrow on 20A. As I recall it, the public expected Arrow on Intel up until launch day.

They announced cancellation of 20A a couple months before Arrow Lake launched, leading to the presumption that it would go to TSMC.

https://www.tomshardware.com/pc-com...-goes-with-external-nodes-instead-likely-tsmc
​

This might've been the last they said about Arrow Lake on 20A:

https://www.tomshardware.com/news/i...er-with-20a-process-node-chips-arrive-in-2024
​

20A was something of a special case, because they only had one announced product on it and weren't offering it to foundry customers. So, aside from the hit they took outsourcing the CPU tile to TSMC, Intel could cancel 20A with little consequence. None of these factors apply to 18A. If Intel cancels that, all hell would break loose and confidence in Intel's foundry among investors and customers would probably collapse.

They also never said why they cancelled it, exactly. I think they cast it as a decision based on resources, which could be referring to many things, but presumably the point is they wanted to focus said resources on 18A.

I would also say packaging has been a bright spot while node advancement has not.

It didn't work out great for Ponte Vecchio. We also don't know how much of Sapphire Rapids' extensive delays were related to that.

Let me ask this... what is Intel's most advanced healthy node? ..and by healthy I mean profitable to produce low margin consumer chips in high volume.

They just did a respin of Meteor Lake on Intel 3. Confusingly, they're offering it under the label of Arrow Lake, but the architecture is 100% Meteor Lake. @thestryker pointed out that it's clocking considerably better, within the same TDP, than Meteor Lake did on Intel 4.

you could make an argument for Intel 7 (renamed to 4), but not in the 60% margin territory that have historically aimed for.

First, it was 7 nm that got renamed to "Intel 4". "Intel 7" was previously called 10nm ESF.

Second, I don't think you could call Intel 4 a healthy situation. In fact, it might've been that very experience they were looking not to repeat with Intel 20A.

https://www.reddit.com/r/hardware/comments/1ehygvl/report_intel_meteor_lake_in_short_supply_due_to/

It sounds like Intel 3 is still ramping and only for high margin products.

Recently less high-margin, given they just cut prices on Xeon 6:

https://www.tomshardware.com/pc-com...ashes-prices-of-xeon-6-cpus-by-up-to-usd5-340
​

Oh, and here's the Meteor Lake node shrink I mentioned. Notice where the Lithography is listed as Intel 3. I forget which two models @thestryker compared, to show the clock speed difference.

https://www.intel.com/content/www/u...-12m-cache-up-to-4-80-ghz/specifications.html
​

Unless they have an absolutely brilliant breakthrough, I wouldn't expect 18a to yield well enough for consumer chips this year. I would love to be wrong, but that's what the indicators are saying to me.

At this point, you're directly contradicting them.

 

[thestryker]

It didn't work out great for Ponte Vecchio.

Part of the problem here was that they didn't have proper validation so they couldn't test the separate parts which was causing compounding yield problems. I'm still not sure who signed off on that, but to me that sounds more like a management type "it's faster this way right?" decision than anything the engineers would want.

Oh, and here's the Meteor Lake node shrink I mentioned. Notice where the Lithography is listed as Intel 3. I forget which two models @thestryker compared, to show the clock speed difference.

165U vs 265U:
https://www.intel.com/content/www/us/en/products/compare.html?productIds=241859,237329

 

[bit_user]

Part of the problem here was that they didn't have proper validation so they couldn't test the separate parts which was causing compounding yield problems. I'm still not sure who signed off on that, but to me that sounds more like a management type "it's faster this way right?" decision than anything the engineers would want.

They probably skipped pre-integration testing for lack of time and to try and make their latest deadlines for Aurora, but still missed those anyhow and ended up shooting themselves in both feet.

Still, we don't know how much of the final yield rate on Ponte Vecchio was due to pre-validation vs. integration problems. Since there are hardly any other examples of stacking active dies on each other (Lakemont is the only one that comes to mind), perhaps their newer generation of Foveros (?) was partly to blame.

 

[JayNor]

Clearwater Forest will have SRAM on the base tile according to Intel's paper.

According to Intel, the Sierra Forest sales haven't been what they expected. The 288 core Sierra Forest is in production now, according to the most recent news. A 288 core Panther Lake Xeon chip was somewhere on a roadmap. Probably makes sense for it to be moved out.

I'm guessing some combination of the new high density SRAM cells and the new hybrid bonding advanced packaging are contributing to the CWF delay, since those aren't on Panther Lake.