News Intel Demonstrates STT-MRAM for L4 Cache

[Admin]

Intel demonstrated its STT-MRAM acting as an L4 cache.

Intel Demonstrates STT-MRAM for L4 Cache : Read more

 

[jimmysmitty]

4th paragraph down you said 20nm I am sure you meant 20ns.

 

[Rdslw]

now lets talk numbers. 2MB does not seem impressive.
BUT its just POC, if they can make it to 300MB+ (like epics L3) and as mentioned 20ns @ 2MB that scales same way as L3 does, now that would be something in my eyes.
its up to them now how generously L4 will be used, and how it affects real live performance.

 

[bit_user]

Intel reported a 20nm write time, 4ns read time, endurance of 1012 cycle

As noted above, the units on the first metric should certainly be ns. However, I'm more puzzled & troubled by the endurance figure...

 

[bit_user]

now lets talk numbers. 2MB does not seem impressive.
BUT its just POC, if they can make it to 300MB+ (like epics L3) and as mentioned 20ns @ 2MB that scales same way as L3 does, now that would be something in my eyes.
its up to them now how generously L4 will be used, and how it affects real live performance.

It seems to me that the main advantages of MRAM are its size and power. Here, being a semi-passive technology could be a huge win for energy efficiency. Both serve as constraints on scaling cache sizes, using current technology.

 

[Rdslw]

It seems to me that the main advantages of MRAM are its size and power. Here, being a semi-passive technology could be a huge win for energy efficiency. Both serve as constraints on scaling cache sizes, using current technology.

thanks, I did not notice power is such an issue in this case, as its constantly refreshed. Then it becomes semi-constant (propably we could idle on half the current power or even lower?). Even more reasons to wait to see real results.
so AMD is becoming king of killing "heavy LOAD"
while INTEL is trying to be good at IDLE.
interesting times indeed.