Intel engineer discusses their dual-core design

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Archived from groups: comp.sys.ibm.pc.hardware.chips (More info?)

On Thu, 01 Sep 2005 21:04:16 -0500, Del Cecchi wrote:

> keith wrote:
>> On Wed, 31 Aug 2005 12:30:44 -0600, Anne & Lynn Wheeler wrote:
>>
>> <snip>
>>
>>>the other issue was that 3033 eventually showed up on the scene which
>>>was nearly the thruput of half-peak 195 (about even on commercial
>>>codes).
>>
>>
>> Wasn't the 3033 a 3168 on steriods? ...complete with dual I-streams?
>
> Story I heard was it was a card for card remap from MST into HPCL-F MS255.

That was the plan, but it didn't turn out that way. They ended up
using the "amazingly dense" 25 gates per module. Lynn has some links to
this end, IIRC. BTW, I did a few "specials" (clock drivers, mostly) in
MS255. It was amazingly fast for its time.

--
Keith
 
Archived from groups: comp.sys.ibm.pc.hardware.chips,comp.sys.intel,comp.arch (More info?)

> already there. Years? Please! They don't simulate/verify in
> multi-processor environments? *Amazing*!

Like the article says, Intel didn't have the test vectors
or BIST for testing interconnects between the two cores.
That's understandable as Intel was fabricating single-cores prior.
Intel has accumulated a large suite of software diagnostics
to verify SMP scenarios (#LOCK, APIC, cache MESI, etc) back when
the Pentium II introduced built-in SMP logic (and before).