News Intel Foundry Roadmap Update - New 18A-PT variant that enables 3D die stacking, 14A process node enablement

[Admin]

Intel's new CEO Lip Bu-Tan took to the stage at the company's Intel Foundry Direct 2025 event here in San Jose, California to outline the company's progress on its foundry initiative.

Intel Foundry Roadmap Update - New 18A-PT variant that enables 3D die stacking, 14A process node enablement : Read more

 

[Heiro78]

I don't get the naming scheme. I woulda thought the lower the number the better/ smaller architecture

 

[EzzyB]

I keep hearing that 18A is "faster, but less dense." I know the site is almost exclusively interested in whatever is faster! 😁 What is the use case for something that's maybe not quite as fast, but more dense. Just size of the chip? More space for more things on the chip? Maybe cheaper to make?

 

[EzzyB]

I don't get the naming scheme. I woulda thought the lower the number the better/ smaller architecture

Oh that one is easy. Let the old timer tell you! 😜

In the old days "NM" was the measure, in nanometers, of the separation of different components, mainly transistors on a chip. I say the old days because "NM" ceased to have any real meaning around the turn of the century (300 NM nodes.) So that is the standard that was set, and then broken long ago.

Notice in the article Tom's says something like "2nm equivalent." That's because 1.8A of 2.0 or whatever aren't really accurate anymore. It's marketing.

A half decade ago or so there was a big hullabaloo about how TMCS had advanced to "7nm", but Intel was stuck on "10 NM". But, if you looked at the chips, while not exactly the same, they were, in fact quite comparable.

So, in the beginning the naming scheme was about the size of features on the chips. The smaller the size the more features you could put on the chip. But, as I said. It's really misleading now. I think we're actually somewhere around 17-20 actual nanometers still even though the branding has gotten away from all companies involved.

 

[DS426]

I keep hearing that 18A is "faster, but less dense." I know the site is almost exclusively interested in whatever is faster! 😁 What is the use case for something that's maybe not quite as fast, but more dense. Just size of the chip? More space for more things on the chip? Maybe cheaper to make?

Yes, probably more focus on chip features and definitely size of the chip where taking up space on advanced node wafers is getting more and more expensive. This would mean that performance optimization would literally come at the trade-off of higher cost.

 

[User of Computers]

Didn't seem to affect the stock price much lol. Guess investors don't really care about the progress?

 

[Pierce2623]

I keep hearing that 18A is "faster, but less dense." I know the site is almost exclusively interested in whatever is faster! 😁 What is the use case for something that's maybe not quite as fast, but more dense. Just size of the chip? More space for more things on the chip? Maybe cheaper to make?

GPUs would be better on “denser but not quite as fast”.

 

[-Fran-]

Hm... Does the market and investors even believe this?

I'm not asking that in a sarcastic or mean way. I honestly don't know (or think) if people believe Intel can pull this aggresive roadmap, because it is rather aggressive.

Regards.

 

[TerryLaze]

Hm... Does the market and investors even believe this?

I'm not asking that in a sarcastic or mean way. I honestly don't know (or think) if people believe Intel can pull this aggresive roadmap, because it is rather aggressive.

Regards.

What do you think is aggressive about it?!
New node two years after the previous one, that's pretty normal.

 

[jkflipflop98]

Didn't seem to affect the stock price much lol. Guess investors don't really care about the progress?

I've learned a long time ago that investors and analysts are pretty much idiots. They have no idea what's going on. I read "expert analyst" blurbs all the time and they're so far off the target that I can't help but to laugh. And those are the people the investors are listening to. It's literally the blind leading the blind.

 

[jkflipflop98]

I don't get the naming scheme. I woulda thought the lower the number the better/ smaller architecture

For the longest time, the nm metric described the distance from the contact points on the transistor - basically the size you could make the entire transistor. Then at some point in the 2000's it kind of morphed to the smallest structure you could fab. Then it turned into the width of the smallest line you could lithographically imprint. Now it's just lost all meaning whatsoever. Intel was the last holdout that actually measured from contact to contact. We stopped doing that with 7nm and just started going with the flow. If everyone else is going to lie, may as well follow suit.

 

[thestryker]

I keep hearing that 18A is "faster, but less dense." I know the site is almost exclusively interested in whatever is faster! 😁 What is the use case for something that's maybe not quite as fast, but more dense. Just size of the chip? More space for more things on the chip? Maybe cheaper to make?

It depends.

This is the unfortunate truth when talking about process nodes. Whether one is better than the other is a balancing act around performance and power consumption. A more dense process generally has better power consumption properties. That means up to a point a more dense node would likely be better, but once that's passed a faster one is going to be better (the differences in speed/density don't tend to be significant so better is a relative term).

The part of the density discussion that gets glossed over a lot in more general tech media is that full nodes have high performance and high density libraries. It's the latter which TSMC has been consistently ahead of everyone else. I'm unsure if that's just due to their general engineering focus or a business one. Apple had bought out the first run of every major EUV node TSMC has put out until N2 and they predominantly use high density libraries.

 

[thestryker]

I don't get the naming scheme. I woulda thought the lower the number the better/ smaller architecture

It is, but you're not accounting for the A which is 'angstrom' even though this isn't an actual measurement in practice. If Intel continued to base the naming off "nm" this is how the naming would look:

1.4 > 1.8 > 3 > 7 > 12 > 16

TSMC is doing the same where they're going from N2 to A16 which would be N1.6 if they kept the same nomenclature.

 

[sseemaku]

I've learned a long time ago that investors and analysts are pretty much idiots. They have no idea what's going on. I read "expert analyst" blurbs all the time and they're so far off the target that I can't help but to laugh. And those are the people the investors are listening to. It's literally the blind leading the blind.

Intel lost credibility, so investors will want to see revenue guidance to believe anything. Until then, this is all just research, marketing and paper launches.

 

[Rob1C]

They could use Foveros to rebirth the Foveon. A marketing dream, or nightmare.

 

[Garlick_2]

It depends.

This is the unfortunate truth when talking about process nodes. Whether one is better than the other is a balancing act around performance and power consumption. A more dense process generally has better power consumption properties. That means up to a point a more dense node would likely be better, but once that's passed a faster one is going to be better (the differences in speed/density don't tend to be significant so better is a relative term).

The part of the density discussion that gets glossed over a lot in more general tech media is that full nodes have high performance and high density libraries. It's the latter which TSMC has been consistently ahead of everyone else. I'm unsure if that's just due to their general engineering focus or a business one. Apple had bought out the first run of every major EUV node TSMC has put out until N2 and they predominantly use high density libraries.

Just created an account to come say that denser nodes are used for better power consumption, so even though it can be at slower frequency, it is more efficient in how it processes the throughput....ie new ultra processors doing similar workloads in 5-25W TDP on a 2nm process instead of 35-65W of a 4nm process.

Good point on the full nodes, though.

 

[User of Computers]

I've learned a long time ago that investors and analysts are pretty much idiots. They have no idea what's going on. I read "expert analyst" blurbs all the time and they're so far off the target that I can't help but to laugh. And those are the people the investors are listening to. It's literally the blind leading the blind.

I'd say that Ian has a pretty good idea what he's talking about.

 

[usertests]

You'll cowards don't even make X3D CPUs

 

[thestryker]

I'd say that Ian has a pretty good idea what he's talking about.

Ian's very much the exception having come from a science background and then working as a professional tech journalist before doing analyst work. I imagine this is why he was able to get contracts from all the big players very quickly upon starting More Than Moore.

 

[User of Computers]

I keep hearing that 18A is "faster, but less dense." I know the site is almost exclusively interested in whatever is faster! 😁 What is the use case for something that's maybe not quite as fast, but more dense. Just size of the chip? More space for more things on the chip? Maybe cheaper to make?

basically hit the nail on the head. It's mostly down to cost. If you can fit more cells in an area, you can make your part smaller with the same number of cells. In practice there's generally a trade-off in terms of performance (see Zen 5C clocks vs Zen 5).

 

[User of Computers]

Ian's very much the exception having come from a science background and then working as a professional tech journalist before doing analyst work. I imagine this is why he was able to get contracts from all the big players very quickly upon starting More Than Moore.

unrelated note- just saw your build. How are those P44 Pros doing? Has the write cache bug hit them yet? I have one and its write performance is nonexistant.

 

[jp7189]

I've learned a long time ago that investors and analysts are pretty much idiots. They have no idea what's going on. I read "expert analyst" blurbs all the time and they're so far off the target that I can't help but to laugh. And those are the people the investors are listening to. It's literally the blind leading the blind.

The market <is supposed to> react to the expectation of future profits (or lack thereof). I'm not sure anything could be derived about the profitability of today's tech talk. It could be these new processes burn a lot of money and don't turn profitable for what the market will bear in real products.

 

[jp7189]

I for one am happy that we keep hearing more and more about the positive progress of Intel processes. I'm really staring to believe they have a shot at recovering their competitiveness at the leading edge. I'm holding on to some skepticism, but I'm hopeful.

 

[dCasualGamer]

The market <is supposed to> react to the expectation of future profits (or lack thereof). I'm not sure anything could be derived about the profitability of today's tech talk. It could be these new processes burn a lot of money and don't turn profitable for what the market will bear in real products.

yeah, i agree.. market only cares about what happen this and next quarters and spin any news to move the stock prices.

 

[thestryker]

unrelated note- just saw your build. How are those P44 Pros doing? Has the write cache bug hit them yet? I have one and its write performance is nonexistant.

They're both fine, but they've also only been in service for around 5 months. I really wish they'd addressed it, but given the wind down of client I'm unsurprised it hasn't been.