intel hub interface bandwidth (quad pumped?)

[i9-9999k]

i am trying to make sense of the bus width and bandwidth of the intel hub interface (ihi) that connected the g/mch and ich4

according to the official intel spec pdfs:

http://download.intel.com/design/chipsets/datashts/29074201.pdf
http://www.intel.com/content/dam/doc/datasheet/e8870io-server-io-hub-datasheet.pdf

the ihi runs at 66 mhz, over an 8-bit wide bus, providing 266 MB/s

like i said i am trying to make sense of the math here

the only thing that kinda makes sense is that this bus is quad pumped (but i haven't read anything about it be qdr in the intel spec pdfs)

here's the math:

66 mhz * 8-bit wide bus = 528 megabits per second

528 Mb/s / 8 = 66 MB/s (this aint right, this should be 266 MB/s)

okay so lets try it with qdr

528 Mb/s * 4 (qdr) = 2112 Mb/s

2112 / 8 = 264 MB/s (that's closer to 266 MB/s, is this right?)

if i take 266 MB/s and divided it by 4 (qdr), it gives me 66.5 MB/s which translates to 532 Mb/s (that's close to 528 Mb/s, is that right?)

and just to make this wall of text a bit prettier, i'll include this relevant picture:

 

[norsestar]

Page 2-3 of your http://www.intel.com/content/dam/doc/datasheet/e8870io-... lists the data bus as 8 bits wide in the 266MHz clock domain which would be 266MB/s.

 

[i9-9999k]

Page 2-3 of your http://www.intel.com/content/dam/doc/datasheet/e8870io-... lists the data bus as 8 bits wide in the 266MHz clock domain which would be 266MB/s.

hmm yea but that's a different chipset, but the first pdf: http://download.intel.com/design/chipsets/datashts/29074201.pdf

is where i got the first screenshot from, so between the 845gv gmch and ich4 the bus operates at 66 MHz

but the second pdf: http://www.intel.com/content/dam/doc/datasheet/e8870io-server-io-hub-datasheet.pdf

has this

 

[norsestar]

The 845GL datasheet says it talks to ICH4 at 66MHz / 266MB/s. The E8870 datasheet says it talks to ICH4 over an 8-bit bus running at 266 MHz. Putting these together, Hub Interface 1.5 takes a 66 MHz reference clock and pushes data over an 8-bit bus at 266 MHz to give 266 MB/s.

Hub Interface is an Intel-proprietary interconnect so it's not surprising there aren't too many details about it. So yes, your math is correct: Intel just doesn't come out and say the data bus runs at 266 MHz in the ICH4 datasheet.

 

[i9-9999k]

The 845GL datasheet says it talks to ICH4 at 66MHz / 266MB/s. The E8870 datasheet says it talks to ICH4 over an 8-bit bus running at 266 MHz. Putting these together, Hub Interface 1.5 takes a 66 MHz reference clock and pushes data over an 8-bit bus at 266 MHz to give 266 MB/s.

Hub Interface is an Intel-proprietary interconnect so it's not surprising there aren't too many details about it. So yes, your math is correct: Intel just doesn't come out and say the data bus runs at 266 MHz in the ICH4 datasheet.

but it doesn't run at 266 mhz, quad pumping doesn't increase the sinusoid oscillation rate. it just increases the data rate (but i'm sure you already know that, just putting this here for reference)

the proper way to say this would be to use megatransfers (mt/s)

example:

a single bit wide bus operating at 100 mhz with ddr, can transfer 200 mt/s

now most people who don't really understand how this works would say that is a 200 mhz signal because it's ddr. it's like how the fsb of the old northwood p4's was considered to have a 400 mhz signal, even tho it was only 100 mhz with qdr

so this processor has a 100 mhz fsb effectively giving 400 mt/s: http://ark.intel.com/compare/27442

this image is confusing:

it makes it appear as if qdr is just 2 separate ddr signals (requiring 2 wires/conductors)