News Intel might axe the 18A process node for foundry customers, essentially leaving TSMC with no rival — Intel reportedly to focus on 14A

[phead128]

This discussion reminds me of this:

Intel: My business model is predicated on nuclear WW3 over vulnerable Taiwan. Gib free taxpayer money.

Intel: By the way, could TSMC fab 30-40% of my chips in the same powder keg? I worship cash.

Google, AMD, Nvidia: Shucks, if Intel’s doing the danger-dance, count us in! Hello powder keg.

 

[JRStern]

Isn't that exactly what Intel spent more than half a decade doing, with their nodes from 10 nm to "Intel 7"?

They kept shrinking it, too.
Also want to escape the conduction problems that stumped them at 10nm and even some previous nodes.

 

[thestryker]

Intel’s 18A was supposed to launch in late 2024 with high-volume manufacturing in 2025 putting it almost a year ahead of TSMC’s N2.

This is false 18A was always a 2025 node. 20A was supposed to be launching at the end of 2024 in ARL, but was canceled.

https://www.anandtech.com/show/1682...nm-3nm-20a-18a-packaging-foundry-emib-foveros

I also see you citing the Reuters report.

This whole thing about 18A is based on said report if you weren't aware.

 

[shady28]

How do you got the piss off part?!
Those clients already are on 18A ,they have contracts that will be fulfilled.
The article says that intel will stop promoting 18A to (additional) customers and not that they are scrapping it, nvidia and qualcomm are already promoted to so if they decide to use intel they will probably produce for them as well.
They got 3 FABs fitted and if the money they will get from the 3 customers plus what intel themselves will make from their own line is enough to cover those 3 FABs then what's the issue?

Why fit more FABs with 18A tech if you can fit them with 14A instead?

18A done, let's move on.

Why fit FABs with 14A when you can fit them with 12A instead?

This is a never ending cycle. They need to focus on a node, get good at it, and stop buying product from their competitor.

The simple fact is that what is sitting in everyone's CPU, GPU on laptop and on desktop right now is either a TSMC N5 derivative (including N4) or, at best, Intel 4 for some parts of ML. One exception being Zen 5c cores on N3E. The only place we see N3 (and Intel 3) outside of phones is server CPUs.

The next generation of GPUs in 18 months is likely to be on an N3 class node. Ditto for desktop and laptop CPUs, maybe with a few small exceptions like the 5C core is. With Apple and AMD Epyx taking up their N2 production capacity, this is the only logical outcome for 2026.

This means that Intel, with 18A, would be in full swing with an N2 class node - potentially on *everything* including GPU, laptop CPU, desktop CPU - for 12-18 months while everyone else is rolling out N3 class devices. Sure, AMD will have N2 *server* CPUs at about the same time as Intel, but they can win at everything else.

It looks to me like they want to leapfrog TSMC so much, they forgot who their real competition is.

 

[rluker5]

I don't know where I saved the transcript, but on the earnings call in January Holthaus mentioned NVL using both Intel and TSMC. This was contrasting with PTL being Intel, but there's basically no chance PTL is entirely Intel so the implication (she may have even said Compute Tiles, but I don't want to say for sure without seeing the transcript) is that some NVL Compute Tiles will be on TSMC and N2 is the only logical choice for that.

That is a respectable source. Much better than 2 anonymous people familiar with some undisclosed matter like the source for this article.

Here is the relevant quote from that transcript with a little extra for context:
"
John Pitzer -- Corporate Vice President, Investor Relations

Srini, do you have a quick follow-on?


Srini Pajjuri -- Analyst

Yes. A quick one. So, on the 18A Panther Lake, I think in the past, I think, Dave, the comment was that you expect to bring roughly 70% of the die in-house. Is that still the plan? And then is it pretty set in stone that you're bringing it back for sure? Or do you have any flexibility whether to bring back more of the die or less of the die if you need to.

So just trying to understand.

David A. Zinsner -- Executive Vice President, Chief Financial Officer


I'm going to let Michelle answer that because it really is her decision on how she builds her products.

Michelle Holthaus -- Interim Co-Chief Executive Officer

Yes. So, we did move Panther Lake inside of 18A design win. But as I stated before, we look at each generation of products based on what's the right product, what's the right process, what's the right market window and what allows our customers to win. So, for Panther Lake, that was 18A.

And as I said, we're very happy with where we are from a performance and yield perspective at this point in the process. So, that will stay on 18A. Then as you look forward, to our next-generation product for client after that, Nova Lake will actually have die both inside and outside for that process. So, you'll actually see compute tiles inside and outside.


Again, it's about optimizing to what allows us to win in the market, what allows us to win with our customers and optimizing the overall product portfolio because at the end of the day, if our customers are successful, we win, that drives more wafers and Intel foundry and that allows us to win, but I'll continue to have a balance. And as I said, we'll be doing the same look across our data center portfolio as well."



A note about Nova Lake is that is supposed to have at least one configuration of compute tile (8p+16e and maybe a smaller version like Alder Lake had like a 4p+8e tile for example) and a low powered compute island probably on the SOC tile.
If there is a combination of Intel fabbed and TSMC fabbed compute tiles on Nova Lake then there are likely 4 possible combinations of that configuration:
One like MTL where the main compute tile is made by Intel and the SOC that also has some compute cores is made by TSMC. A second where the inverse is true. A third where one fab makes the 8p+16e tile and the other makes the possible 4p+8e tile. And a fourth where some chips just have all of the compute made by one company and all or some compute tiles of other chips are made the other company.

If 18A is comparable to 2nm, then it makes the most financial sense to do the most expensive node in house for the main compute tiles and use a cheaper node from TSMC for the less node critical SOC tile that also has compute on it. Which would follow the first scenario like MTL did.
If there is not enough 18A available and there is ample supply of 2nm, and/or 18A sucks compared to 2nm, all of which seems unlikely then the 2nd scenario is likelier.
The last 2 scenarios seem unlikely but would present interesting comparison opportunities.

 

[jackt]

I think the Administration's focus is simply to have the manufacturing happen on US soil. They don't seem particularly concerned about whether it's TSMC, Intel, or Samsung who owns the plant. I disagree, because ownership of the process IP counts at least as much as the physical plant, but that's just my opinion.

bit_user, are you an AI or a human ?

 

[thestryker]

A note about Nova Lake is that is supposed to have at least one configuration of compute tile (8p+16e and maybe a smaller version like Alder Lake had like a 4p+8e tile for example) and a low powered compute island probably on the SOC tile.

There 3 known configurations 16/32/4, 8/16/4 and 4/8/4. It makes sense that there would be two different Compute Tile configurations: 8/16 and 4/8 as cutting that much down seems excessive and I think a 4/8 tile would be used on both mobile and desktop. The LPE cores are almost certainly on the SoC tile as I cannot think of any reason desktop parts would have them otherwise.

If 18A is comparable to 2nm, then it makes the most financial sense to do the most expensive node in house for the main compute tiles and use a cheaper node from TSMC for the less node critical SOC tile that also has compute on it. Which would follow the first scenario like MTL did.
If there is not enough 18A available and there is ample supply of 2nm, and/or 18A sucks compared to 2nm, all of which seems unlikely then the 2nd scenario is likelier.

I doubt using N2 would be cheaper than 18A so that one seems very unlikely. Depending on the timeline on Fab 62 capacity could still be a very real concern since PTL is certainly still going to be in production when NVL ramps.

 

[PCWarrior]

This is false 18A was always a 2025 node. 20A was supposed to be launching at the end of 2024 in ARL, but was canceled.

https://www.anandtech.com/show/1682...nm-3nm-20a-18a-packaging-foundry-emib-foveros

Not always. What you are citing was the original announcement in 2021. But in April 2022 Intel moved up 18A to H2 2024. https://www.anandtech.com/show/1734...on-moves-up-intel-18a-manufacturing-to-h22024

This whole thing about 18A is based on said report if you weren't aware.

I know. I was just pointing out to someone who accused others of not reading this article that in fact this article filtered out the misinformation he copied – pasted from the original Reuters piece.

 

[thestryker]

Not always. What you are citing was the original announcement in 2021. But in April 2022 Intel moved up 18A to H2 2024.

That must have been the shortest launch shift they've ever had because it was never mentioned again and all of the 18A product announcements were 2025. Makes me wonder which financial person signed off on officially announcing pulling it forward.

 

[bit_user]

They kept shrinking it, too.
Also want to escape the conduction problems that stumped them at 10nm and even some previous nodes.

But, my point was that, after their 10 nm++++ node (i.e. the Raptor Lake version of Intel 7), I think that well had run dry. And yes, by my count, there were actually 5 iterations on their 10 nm node (hence the 4x +'s).

 

[bit_user]

The simple fact is that what is sitting in everyone's CPU, GPU on laptop and on desktop right now is either a TSMC N5 derivative (including N4) or, at best, Intel 4 for some parts of ML. One exception being Zen 5c cores on N3E. The only place we see N3 (and Intel 3) outside of phones is server CPUs.

First of all, Intel ported the Meteor Lake compute die to Intel 3 and launched it as a lower-end part of the Arrow Lake mobile lineup. If you look at the product specs, you'll know which ones these are by looking at where it says "CPU Lithography: Intel 3". For instance:

https://www.intel.com/content/www/u...-12m-cache-up-to-4-90-ghz/specifications.html
​

Secondly, this brings us to the place where you see TSMC N3B, which is in the Lunar Lake and the rest of the Arrow Lake lineup. Not sure how you completely missed that. Again, look where it says "CPU Lithography":

https://www.intel.com/content/www/u...-36m-cache-up-to-5-70-ghz/specifications.html
​

 

[bit_user]

bit_user, are you an AI or a human ?

Artificial intelligence is no match for my natural stupidity!
: D

 

[thestryker]

there were actually 5 iterations on their 10 nm node

4, but there had been 5 on the roadmap at one point and I'm not sure what happened there.

10nm - CNL
10nm/+ - ICL
10nm+/++/SF - TGL
10nm++/+++/ESF/Intel 7 - ADL/RPL

 

[bit_user]

4, but there had been 5 on the roadmap at one point and I'm not sure what happened there.

10nm - CNL
10nm/+ - ICL
10nm+/++/SF - TGL
10nm++/+++/ESF/Intel 7 - ADL/RPL

Intel made further changes between ADL and RPL, which I think had a lot to do with V/F curve reductions essential for Raptor Lake's higher frequency scaling. I count that as the 5th. Back in the 14 nm era, I think changes on that scale definitely would've merited another "+".

 

[JRStern]

But, my point was that, after their 10 nm++++ node (i.e. the Raptor Lake version of Intel 7), I think that well had run dry. And yes, by my count, there were actually 5 iterations on their 10 nm node (hence the 4x +'s).

Intel 10/7 is already too late, it's dual/quad DUV, right?
Something like 28nm is the last single-exposure DUV, want to see what they can do today with 28nm+++++.

 

[bit_user]

Something like 28nm is the last single-exposure DUV, want to see what they can do today with 28nm+++++.

First, I didn't know Intel had a 28 nm node. Sandybridge was 32 nm, then Ivybridge was 22 nm.

Second, even if they could refine 32 nm or 22 nm, what would be the point? How much better do you think it could really be and why?

 

[thestryker]

Second, even if they could refine 32 nm or 22 nm, what would be the point? How much better do you think it could really be and why?

They did just that: Intel 16 is a refined and standardized 22nm.

https://www.anandtech.com/show/18957/intel-foundry-services-readies-intel-16-fabrication-process

 

[JRStern]

First, I didn't know Intel had a 28 nm node. Sandybridge was 32 nm, then Ivybridge was 22 nm.

Second, even if they could refine 32 nm or 22 nm, what would be the point? How much better do you think it could really be and why?

I don't know how much better they could be. Certainly Intel could go back and design for lower power than they did. Based on later work they might be able to now get the same performance on half the power, or less, that's pretty certain. They might be able to get great yields on much larger chips, monolithic chips instead of chiplets, regaining another advantage, at least equaling the additional complexity they had hoped to get with shrinking geometries but have largely been unable to because of power and heat and yield issues. Don't have to go through the entire chiplet assembly process. Might be stuck at lower core count, but I'm skeptical that workstation chips, at least, really need high core counts. Server chips with fewer cores can simply sell at lower prices and be ganged on the motherboards, if even that much is needed, it's as much a per-server or per-core licensing issue as it is jamming them all in one package, much better I/O throughput with 4 16-core processors instead of one 64-core processor. An open-ended scale-out capability is probably better than a fixed max of cores on one server anyway. Etc etc etc.

 

[bit_user]

I don't know how much better they could be. Certainly Intel could go back and design for lower power than they did. Based on later work they might be able to now get the same performance on half the power, or less, that's pretty certain. They might be able to get great yields on much larger chips, monolithic chips instead of chiplets,

Even if all that were true, it still wouldn't make those nodes remotely competitive. Also, the yields on their mature nodes tend to be quite high. I think there's really not much to be gained on that front, especially when all of the big chips can disable a couple cores to reach near 100% die utilization.

The glaring thing you're missing is density. That's what enables more cores - and performance scales much better with more cores than more frequency. So, at best those nodes would only be interesting for things like cache and I/O, which is what they're already using old nodes for.

at least equaling the additional complexity they had hoped to get with shrinking geometries but have largely been unable to because of power and heat and yield issues.

Intel 7 doesn't have yield issues, to my knowledge, and is far more efficient than any of the old nodes you're talking about. It's only hot because density increased faster than efficiency. If you really cared about efficiency, you can still run Intel 7 chips at low enough frequency to do better than anything you're talking about.

I'm skeptical that workstation chips, at least, really need high core counts.

They already offer the Xeon W-2000 series CPUs with monolithic dies and reduced core counts.

Server chips with fewer cores can simply sell at lower prices

Again, they have at least two server dies, with I think the smaller one being shared with the lower-end Xeon W.

and be ganged on the motherboards, if even that much is needed,

It makes a lot more sense, both in terms of performance and economics, to have multiple dies in-package than multiple packages. That's why the small die Xeons don't have UPI blocks.

it's as much a per-server or per-core licensing issue as it is jamming them all in one package,

If CPU makers really targeted this niche of software that's supposedly tied to the number of cores per package, rather than the total number of cores, those software vendors would just fix their licensing schedule.

much better I/O throughput with 4 16-core processors instead of one 64-core processor.

Intel already supports 4-way and 8-way scaling on select models, for people who really need that. It's a niche, I'm sure, partly evidenced by AMD's success in spite of ignoring completely it.

The fundamental problem is that you're not doing the math, on any of this. If this stuff made any sense, they'd already have been doing it - especially when they were facing so many problems getting 10 nm online. Any time you think you're smarter than the industry, double-check yourself because you're definitely not. Don't take that personally, but I do think the height of hubris to assume that these companies don't know all the numbers up-and-down, inside-and-out, and would continue to make the investments they do, if there were cheaper and easier ways to be competitive.

 

[JayNor]

read Intel's last two earnings call transcripts. CWF has already booted on 18a. It is scheduled for 1H of 2026.

Intel will build more wafers of Nova Lake in their own foundries than for Panther Lake, according to MJH.

Intel planned to have fab 62 ready to run 18a for this year, but apparently it isn't ready yet. My guess is Intel simply doesn't have enough 18a fab capacity for their own products, so it doesn't make sense for them to seek more external customers.

 

[JRStern]

The fundamental problem is that you're not doing the math, on any of this. If this stuff made any sense, they'd already have been doing it - especially when they were facing so many problems getting 10 nm online. Any time you think you're smarter than the industry, double-check yourself because you're definitely not. Don't take that personally, but I do think the height of hubris to assume that these companies don't know all the numbers up-and-down, inside-and-out, and would continue to make the investments they do, if there were cheaper and easier ways to be competitive.

But I think they may do the math and they may follow my advice, wait and see.

I don't have the hard numbers, but maybe they don't either. I tend to buy Intel processors with slower clocks and relatively fewer cores, around the -i5 level, and have been very happy with them. I haven't gotten to choose a lot of server chips in many years, on Azure they won't even tell you what you're on much of the time, but on a lot of public or private cloud systems I've spent beaucoup time in tuning exercises trying to undo or at least diagnose all sorts of noisy neighbor problems, not to mention crazy core pricing algorithms. All I talk about has some pretty hard math behind it.

A great deal of IT is done that does not stress performance or price/performance or need to manage scale issues. I've mostly worked where we did have those, bigtime. For the 95% that's soft and slow none of this matters.

But scalability has been flat to negative since DUV, what with fab difficulty, conduction, heat, bottlenecks, etc. Chiplets have a cost, TANSTAAFL. Physics has just not allowed nodes to scale down without exponentially increasing problems.

We'll just have to wait and see. In ten years we could be back to 100% DUV. Big freaking packages but monolithic inside.

Or not.

 

[thestryker]

But scalability has been flat to negative since DUV, what with fab difficulty, conduction, heat, bottlenecks, etc. Chiplets have a cost, TANSTAAFL. Physics has just not allowed nodes to scale down without exponentially increasing problems.

We'll just have to wait and see. In ten years we could be back to 100% DUV. Big freaking packages but monolithic inside.

Never going to happen because density is a massive problem (if you look at the high density EUV nodes they're significantly ahead of DUV). Had 450mm wafers become a thing there would be a chance for something like this, but it's dead and isn't coming back (and there are a lot of AI companies who are probably very angry about that).

 

[Pigpig]

Was Broadcomm the only one actually getting chips from Intel Foundries? Am I forgetting others?

I ask, because, at some point, they'll have to commit to a particular node and deliver so clients and Intel can fine tune the relationships on how to deliver the nodes. What I see here is rather dangerous. While I understand, at a high level, why it is being done, I can't shake the feeling that he's gambling big time with this. I'm not sure how "big" the side-step to the new node is and how the conversations with potential node clients are, but I wouldn't be surprised that Intel had to cave to the pressure at the expense of gambling they'll be able to pull off 14A for customers. Also, given the costs, how big the clients have to be in order to turn a profit?

Risky as all hell, if you ask me.

Regards.

No, the 18A external customers are amazon and Microsoft, base on rumours Intel is stop to promote 18A to new customers, but doesn't mean they are scrapping 18a foundry, 18A still be used in Intel product. and old promised customers

 

[phead128]

So when Pat said: "I've bet the whole company on 18A", he really meant he bet the company on 14A and 10A.

 

[JRStern]

if you look at the high density EUV nodes they're significantly ahead of DUV

If something has half the yield is it ever really ahead?
OK the last DUV nodes had poor yield too, that's why I say have to go further back, to single mask.
Maybe 99% yield beats 15% yield in price/performance.
Only has to be half as fast.
Scale out instead of down.