Intel Patents Forming MP Chips Using Dual Processors

[Guest]

Intel has received a patent covering its technology to create multi-core processor packages from individual dual-core processors.

Intel Patents Forming MP Chips Using Dual Processors : Read more

 

[Parsian]

isnt this the method they used to make the Core 2 Quads?

 

[madooo12]

[citation][nom]Parsian[/nom]isnt this the method they used to make the Core 2 Quads?[/citation]

Filed in April 2007

 

[husker]

It does appear to simplify the architecture, but this type of simplification usually comes at a cost of speed and efficiency. I'm wondering if it will scale well with a large number of processors since it requires a point to point link between all processors this could get out of hand in a hurry.

 

[ojas]

[citation][nom]Parsian[/nom]isnt this the method they used to make the Core 2 Quads?[/citation]
Probably been using it already, just that the patent was granted now.

 

[eddieroolz]

[citation][nom]husker[/nom]It does appear to simplify the architecture, but this type of simplification usually comes at a cost of speed and efficiency. I'm wondering if it will scale well with a large number of processors since it requires a point to point link between all processors this could get out of hand in a hurry.[/citation]

That may have been true for the days of FSB that were bottlenecking single processors, let alone dual. However, with the days of QPI buses this might not be such a big issue.

 

[DjEaZy]

... it's like hypertransport in a sense...

 

[bigdog44]

The first diagram looks like a pentagram on homebase... is SIntel patenting its' business model?

 

[willard]

[citation][nom]DjEaZy[/nom]... it's like hypertransport in a sense...[/citation]
Yeah, in the same way that a car is like a road.

Hypertransport is a method of interconnecting chips. This patent is for what you can do with interconnected chips.

 

[madooo12]

[citation][nom]bigdog44[/nom]The first diagram looks like a pentagram on homebase... is SIntel patenting its' business model?[/citation]
can you patent to be evil, a big monopoly and an anti-competitive company? don't answer that

 

[husker]

[citation][nom]eddieroolz[/nom]That may have been true for the days of FSB that were bottlenecking single processors, let alone dual. However, with the days of QPI buses this might not be such a big issue.[/citation]
Good point.

 

[doive1231]

This will stop AMD in their tracks.

 

[blazorthon]

Intel used this method for Core 2 Quads and the Xeons of the time. In fact, Intel has been using this for their Nehalem CPUs with more than 4 cores and more. Guess what? AMD does it too. AMD does this for the Magny-Cours and Interlagos Opterons. So, is AMD going to get a big FU in the mail from Intel soon, inviting AMD to a party in a court house with this as the theme?

 

[blazorthon]

[citation][nom]blazorthon[/nom]Intel used this method for Core 2 Quads and the Xeons of the time. In fact, Intel has been using this for their Nehalem CPUs with more than 4 cores and more. Guess what? AMD does it too. AMD does this for the Magny-Cours and Interlagos Opterons. So, is AMD going to get a big FU in the mail from Intel soon, inviting AMD to a party in a court house with this as the theme?[/citation]

Intel also used it for their dual core Netburst chips.

 

[ProDigit10]

oh no, it's a demon star ring bus!

 

[nukemaster]

Some of this DOES look allot like AMD's NUMA setup.

Now here Intel seems to be doing thing different(Not using HT and using the cpu substrate).

This is far more then just joining cpus.

 

[elbert]

I don't see how Intel can patent reed's Law for full interconnection. This looks to me like a mesh topology with a star network topology to the ICH. I can see why these methods are used due to similar nature for more cores or PC but why make them out to be something new.

 

[blazorthon]

[citation][nom]nukemaster[/nom]Some of this DOES look allot like AMD's NUMA setup.Now here Intel seems to be doing thing different(Not using HT and using the cpu substrate).This is far more then just joining cpus.[/citation]

Interlagos is two Valencia 4, 6, or 8 core dies connected to each other in a single package, just like Core 2 Quads and the other examples that I listed. It's the same as this patent, except the bus interface (QPI vs. HT) is different and maybe a few other minor differences.

 

[A Bad Day]

[citation][nom]husker[/nom]It does appear to simplify the architecture, but this type of simplification usually comes at a cost of speed and efficiency. I'm wondering if it will scale well with a large number of processors since it requires a point to point link between all processors this could get out of hand in a hurry.[/citation]

I suppose it works fairly well when you have like 2-4 processors. Once you go past like a dozen of processors with the point-to-point system, you're going to need lots of wiring and anti-crosstalk measures.

 

[blazorthon]

[citation][nom]A Bad Day[/nom]I suppose it works fairly well when you have like 2-4 processors. Once you go past like a dozen of processors with the point-to-point system, you're going to need lots of wiring and anti-crosstalk measures.[/citation]

Make it more modular. Up to four processors could be a single linked up group and then up to 16 could be a linked group of four modules and so on. That could help it a little.

 

[jimmysmitty]

[citation][nom]blazorthon[/nom]Intel used this method for Core 2 Quads and the Xeons of the time. In fact, Intel has been using this for their Nehalem CPUs with more than 4 cores and more. Guess what? AMD does it too. AMD does this for the Magny-Cours and Interlagos Opterons. So, is AMD going to get a big FU in the mail from Intel soon, inviting AMD to a party in a court house with this as the theme?[/citation]

Thats not quite right. Westmere was the first 6 core from Intel, it was a 32nm die shrink of Nehalem. It was a monolithic die, not MCM like Core 2 Quad or Pentium D.

Nehalem-EX was the first 8 core CPU and it as well is also a monolithic design, not MCM. In fact Nehalem EX is currently Intels largest CPU in terms of die size and amount of cores in the CPU itself. None of Intels current CPUs are MCM, they have SMT which allows multiple threads per core but thats it.

AMDs 12 core is two Thuban 6 cores in a MCM package much like Core 2 Quad but Intel is not going to do that again for a while, except with possibly Haswell and the L4 Cache.

 

[jackbling]

MARK OF THE BEAST

 

[tomfreak]

so they gonna manufacture i3 CPU only and put 4 of them together call it i7 with 8 cores?

Much cheaper this way but hopefully I can cheaper CPU in the future across the entire line of Intel processor.

 

[sykozis]

[citation][nom]Parsian[/nom]isnt this the method they used to make the Core 2 Quads?[/citation]
It's very similar. Also just a modification of how they made the Pentium-D.... Also similar to what AMD is doing with Bulldozer

 

[blazorthon]

[citation][nom]jimmysmitty[/nom]Thats not quite right. Westmere was the first 6 core from Intel, it was a 32nm die shrink of Nehalem. It was a monolithic die, not MCM like Core 2 Quad or Pentium D.Nehalem-EX was the first 8 core CPU and it as well is also a monolithic design, not MCM. In fact Nehalem EX is currently Intels largest CPU in terms of die size and amount of cores in the CPU itself. None of Intels current CPUs are MCM, they have SMT which allows multiple threads per core but thats it.AMDs 12 core is two Thuban 6 cores in a MCM package much like Core 2 Quad but Intel is not going to do that again for a while, except with possibly Haswell and the L4 Cache.[/citation]

I didn't say anything about the Sandy chips because I didn't think that any of them were MCM packages. My bad on some of the Nehalem chips.

Point mainly was that AMD does this too and what will happen to AMD for it now that Intel seems to have patented. Or, did Intel only patent the way that they do it?