News Intel Ponte Vecchio and Xe HPC Architecture: Built for Big Data

Intel999

Honorable
Jan 13, 2015
17
2
10,525
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Maybe if Ponte Vecchio had been ready in 2018, when it was suppose to be, it would be shipping in the first exascale computer.

However, since AMD confirmed that MI200 accelerators started shipping in Q2 for implementation in an exascale computer it seems Ponte Vecchio might be in the second exascale computer and still slower than the first one.

That "first exascale computer" comment might be coming from an old Intel propaganda sheet. This whole article sounds like regurgitated Intel double speak.

If you are going to brag about Intel's 8 way GPU to GPU connectivity why not compare the FP64, BF16 etc. performance to Nvidia's 8 way communicating GPUs that have been shipping for two years? By the time, Ponte Vecchio ships the Nvidia option will have been out for 3 years. Worse than that, an updated version from Nvidia will be out.

Typical Intel, look at we have! in the future, maybe.
 
Reactions: fball922

JayNor

Commendable
May 31, 2019
299
42
1,710
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Strange that Xe-Link is responsible for coherency in today's presentations. I recall discussions of CXL maintaining coherency being a feature, but didn't see CXL discussed today.
 

waltc3

Commendable
Aug 4, 2019
209
101
1,760
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Let's hope that Intel isn't going to try and texture across the PCIe bus as its i7xx GPUs were hobbled with texturing across the AGP bus--if so, then these won't really be competitive at all (as the i7xx GPUs weren't competitive with 3dfx or nVidia GPUs at the time, who both textured from their far faster onboard memory.) This is tongue 'n cheek because I really do not expect Intel to make such a fundamental mistake again, but it does bear a comment, imo.
 

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