News Intel Powers On Sapphire Rapids Processors, Scheduled for 2021

[Admin]

Intel announced that it has finished power on testing of its Sapphire Rapids processors with new AMX technology.

Intel Powers On Sapphire Rapids Processors, Scheduled for 2021 : Read more

 

[Deicidium369]

"It does appear, though, that the Sapphire Rapids chips will be the first general-purpose data center processors from Intel that will propel the company beyond its support for the PCIe 3.0 interface"

Really? So Sapphire Rapids coming out BEFORE Ice Lake SP? Ice Lake SP has 64 PCIe4 channels in a single socket config, and 128 PCIe4 channels in dual socket - the same # as Epyc.

"That will address a weakness that Intel faces against AMD's PCIe 4.0 EPYC Rome processors that are already on the market"

Niche market at best - Intel Whitley will be mass market and will usher in mainstream PCIe4 usage.

 

[vinay2070]

I finish reading the article and scroll down to the comments section, just when I start reading the comments, they move down because of some other links start popping up in place. Then you have to start scrolling down with uncertainity not knowing how long you have to scroll down. If there are no comments or a single liner comment, you might miss when scrolling down and then you keep wondering where the heck are the comments. What a mess! Whoever designed this site, didnt make it user friendly. They just want users to go elsewhere and read.

 

[JayNor]

AMD's proposal for every solution has been more hammers. Perhaps in zen4 we'll see avx512, but now we learn Intel will implement matrix operations on the CPU in the same timeframe ... It appears AMD is willing to let Intel lead the way on the new features.

Conversely, Intel hasn't countered with a 64 core server chip of their own. They seem to be content with providing 4 and 8 socket solutions, and can bundle that with Optane DIMMS for huge memory solutions. Lisa Spelman's video today had a slide showing over 270 design wins advancing to production for Optane ... which also implies Intel Server chips. AMD has no answer.

 

[Deicidium369]

AMD's proposal for every solution has been more hammers. Perhaps in zen4 we'll see avx512, but now we learn Intel will implement matrix operations on the CPU in the same timeframe ... It appears AMD is willing to let Intel lead the way on the new features.

Conversely, Intel hasn't countered with a 64 core server chip of their own. They seem to be content with providing 4 and 8 socket solutions, and can bundle that with Optane DIMMS for huge memory solutions. Lisa Spelman's video today had a slide showing over 270 design wins advancing to production for Optane ... which also implies Intel Server chips. AMD has no answer.

Well, AMD has been destroying Intel for going on 30 years now - and while x64 was great - how long ago was that? Intel leads, AMD tries to follow.

Well the shipping non existent 10nm has been available for purchase in premium devices for going on 9 months now - and Intel will deliver Tiger Lake premium designs around October - just like Ice Lake did a year before. and the non existent 10nm+ will give us 38C Ice Lake SP with upto 128 PCIe4 lanes in a dual socket system... at some point this year the nonexistent 10nm+ will also deliver a desktop GPU and a compute focused GPU for data centers - and that's just Xe HP - not even a pale shadow to Xe HPC. Amazing how much revenue will be made by selling all those nonexistent 10nm products.

The 900# Gorilla has woken up and doesn't like seeing a Capuchin monkey in it's cage. The window for AMD to capitalize on the 900# Gorilla being docile is over.

I can hear them now - I am too optimistic about Intel - that AMD something something profit...

 

[bit_user]

Intel will deliver Tiger Lake premium designs around October - just like Ice Lake did a year before. and the non existent 10nm+ will give us 38C Ice Lake SP with upto 128 PCIe4 lanes in a dual socket system... at some point this year the nonexistent 10nm+ will also deliver a desktop GPU and a compute focused GPU for data centers - and that's just Xe HP - not even a pale shadow to Xe HPC. Amazing how much revenue will be made by selling all those nonexistent 10nm products.

To paraphrase the saying: "don't count your chips before they've launched."

Ice Lake SP is how many years late? And still not out?

The 900# Gorilla has woken up and doesn't like seeing a Capuchin monkey in it's cage.

It might've woken up, but hasn't even gotten out of bed, yet.

 

[bit_user]

AMD's proposal for every solution has been more hammers. Perhaps in zen4 we'll see avx512, but now we learn Intel will implement matrix operations on the CPU in the same timeframe ... It appears AMD is willing to let Intel lead the way on the new features.

Um, "more hammers" would be an apt description of how Intel keeps trying to pack its CPUs with features to compete with GPUs. I was moved to groan, at the mention of AMX.

They never learn, it seems. ...even after buying three different AI chip makers (Movidius, Nervana, and Habana Labs) and launching an indigenous dGPU effort!

 

[jeremyj_83]

and the non existent 10nm+ will give us 38C Ice Lake SP with upto 128 PCIe4 lanes in a dual socket system

The "up to" is the most important part in that entire statement. That means there will be varieties that will not support 64 lanes/CPU. If you need more lanes you have to spend a lot more on the CPUs or get more cores that you need. I wouldn't be surprised if Intel goes and keeps the 64 lane variants for the Platinum only, Gold 48, Silver 36, and Bronze 24. Would be a great way for them to force people to buy more CPU if they need more IO.

 

[bit_user]

The "up to" is the most important part in that entire statement.

Or, how about the part where Intel is putting a <= 38-core/64-lane part against a 64-core/130-lane CPU?

Good luck with that, Intel. If Ice Lake SP were half as good as @Deicidium369 makes them sound, Nvidia would've surely used them in the DGX A100.

 

[TerryLaze]

I was moved to groan, at the mention of AMX.

They never learn, it seems. ...even after buying three different AI chip makers (Movidius, Nervana, and Habana Labs) and launching an indigenous dGPU effort!

Nobody design CPUs for you, or me, or any one of us.
For intel to put this in they had enough demand for it from their customers.
This is how intel sells everything they can produce.

 

[bit_user]

Nobody design CPUs for you, or me, or any one of us.

I'm not even talking about me. I'm talking about AVX-512 being a bad move for them, and they're just continuing the trend with AMX.

For intel to put this in they had enough demand for it from their customers.

How do you even know that? Do you work there?

I don't think it came out of nowhere, but it's one thing to see a market need for matrix arithmetic acceleration, and another thing to decide it belongs in a CPU.

This is how intel sells everything they can produce.

Oh, you mean like Xeon Phi? No, Intel is not perfect. Sorry to show you the hard truth.

Intel is still acting like x86 CPU is the best solution to all problems, in spite of what the Phi showed them.

You're confusing strong financial results with sound strategy. Back in 2000, there were a lot of tech companies that did phenomenally well, just by being in the right market at the right time. Good fortune can cover for a lot of strategic and tactical missteps.

 

[Deicidium369]

The "up to" is the most important part in that entire statement. That means there will be varieties that will not support 64 lanes/CPU. If you need more lanes you have to spend a lot more on the CPUs or get more cores that you need. I wouldn't be surprised if Intel goes and keeps the 64 lane variants for the Platinum only, Gold 48, Silver 36, and Bronze 24. Would be a great way for them to force people to buy more CPU if they need more IO.

Yes there will be variants with less than 64 per socket - the rest of your post is conjecture. Kinda worried that what little advantage AMD had is pretty much gone?

 

[Deicidium369]

I'm not even talking about me. I'm talking about AVX-512 being a bad move for them, and they're just continuing the trend with AMX.


How do you even know that? Do you work there?

I don't think it came out of nowhere, but it's one thing to see a market need for matrix arithmetic acceleration, and another thing to decide it belongs in a CPU.


Oh, you mean like Xeon Phi? No, Intel is not perfect. Sorry to show you the hard truth.

Intel is still acting like x86 CPU is the best solution to all problems, in spite of what the Phi showed them.

You're confusing strong financial results with sound strategy. Back in 2000, there were a lot of tech companies that did phenomenally well, just by being in the right market at the right time. Good fortune can cover for a lot of strategic and tactical missteps.

Intel sold quite a few PHI - I know when someone states facts that Intel is a high volume manufacturer and AMD is at best niche - you pull out stuff that is ancient and EOLd... a sound strategy tends to lead to stong financials ...

 

[Deicidium369]

Or, how about the part where Intel is putting a <= 38-core/64-lane part against a 64-core/130-lane CPU?

Good luck with that, Intel. If Ice Lake SP were half as good as @Deicidium369 makes them sound, Nvidia would've surely used them in the DGX A100.

Well since they 128 lanes on the AMD is dual socket, the Intel would be dual socket as well. Epyc has 128 lanes per CPU - but 64 are used for CPU to CPU communications.

Dual Socket Ice Lake SP - 128 PCIe4 Lanes
Dual Socket Epyc - 128 PCIe4 Lanes

 

[Deicidium369]

Well since they 128 lanes on the AMD is dual socket, the Intel would be dual socket as well. Epyc has 128 lanes per CPU - but 64 are used for CPU to CPU communications.

Dual Socket Ice Lake SP - 128 PCIe4 Lanes
Dual Socket Epyc - 128 PCIe4 Lanes

And as far as Nvidia choosing AMD - AMD probably paid Nvidia to use it's systems - and Nvidia knows the writing on the wall - that Intel is coming for their Crown.

 

[PCWarrior]

Intel sold quite a few PHI - I know when someone states facts that Intel is a high volume manufacturer and AMD is at best niche - you pull out stuff that is ancient and EOLd... a sound strategy tends to lead to stong financials ...

Deicidium369 – My advice to you, and this is a general advice, is to simply avoid arguing with certain individuals on here (and any forum for that matter), no matter how tempting it is to respond to them. You are just wasting your time arguing with them - they will drag you into an endless pointless debate where you will have to set the record straight with each response - a very time consuming process. Remember it is much easier for them to throw some fact-less non-sense than for you to properly dispel it. Don’t fall into that trap.

 

[jeremyj_83]

Yes there will be variants with less than 64 per socket - the rest of your post is conjecture. Kinda worried that what little advantage AMD had is pretty much gone?

The only conjecture is guessing on the PCIe lane distribution.

Well since they 128 lanes on the AMD is dual socket, the Intel would be dual socket as well. Epyc has 128 lanes per CPU - but 64 are used for CPU to CPU communications.

Dual Socket Ice Lake SP - 128 PCIe4 Lanes
Dual Socket Epyc - 128 PCIe4 Lanes

Depending on how Dell, HP, etc.. wants it setup, Dual Socket Gen 2 Epyc can have 160 PCIe lanes for IO with a minimum of 128 lanes. Even in the 160 lane setup, CPU-CPU communication will have 96 PCIe 4 lanes which is at least 50% more bandwidth than 6 UPI lanes.

 

[bit_user]

Yes there will be variants with less than 64 per socket

Maybe not? Show me a LGA3647 Xeon with fewer than 48. I haven't seen one.

The only exception I've seen to 48 lanes in that socket is the single-CPU Xeon-W flavors that have 64 lanes, because they repurposed some of the UPI pins.

 

[bit_user]

you pull out stuff that is ancient and EOLd...

You don't cancel a hugely successful product line. And Phi is not ancient history, as it was fianlly EOL'd only 1 year ago.

https://www.anandtech.com/show/14305/intel-xeon-phi-knights-mill-now-eol

Furthermore, Phi is directly relevant to my point, because it's an example of Intel trying to do things with x86 that don't make sense for it.

AVX-512 has basically been a mess, and AMX seems like yet another example of Intel not knowing when to leave well-enough alone. Of course, it's for AMD if Intel continues to make their cores ever-larger and more complex.

 

[bit_user]

And as far as Nvidia choosing AMD - AMD probably paid Nvidia to use it's systems

Got proof?

Oh, that's right. You never post proof.

 

[bit_user]

they will drag you into an endless pointless debate where you will have to set the record straight with each response - a very time consuming process. Remember it is much easier for them to throw some fact-less non-sense than for you to properly dispel it. Don’t fall into that trap.

He's the one dragging endless debates. And he doesn't set any record straight, as he only posts speculation, conjecture and muddled memories - never citing any sources for his claims.

You are not helping.

 

[bit_user]

Well since they 128 lanes on the AMD is dual socket, the Intel would be dual socket as well. Epyc has 128 lanes per CPU - but 64 are used for CPU to CPU communications.

Dual Socket Ice Lake SP - 128 PCIe4 Lanes
Dual Socket Epyc - 128 PCIe4 Lanes

Single Socket Epyc - 128 PCIe4 Lanes, as well.

Anyway, I don't get how this is winning - Intel has to go dual-socket for 128 lanes, yet that gives them only 76 cores (allegedly) vs. AMD's 128.

 

[jeremyj_83]

He's the one dragging endless debates. And he doesn't set any record straight, as he only posts speculation, conjecture and muddled memories - never citing any sources for his claims.

You are not helping.

Who is not helping?

 

[jeremyj_83]

Got proof?

Oh, that's right. You never post proof.

Even easier than AMD paying nVidia is that Intel didn't have any PCIe 4.0 CPUs. Without PCIe 4.0 the new nVidia systems won't work. What is even more ironic is that Intel might have validated their PCIe 4.0 SSDs on Gen 2 Epyc platform. Servethehome has an interesting write-up about the 3rd Gen Xeon Scaleable and PCIe support.

 

[bit_user]

Even easier than AMD paying nVidia is that Intel didn't have any PCIe 4.0 CPUs.

Ice Lake-SP was rumored to be sampling to industry partners as early as late last year. Nvidia might've been able to use them, if they really wanted.

Servethehome has an interesting write-up about the 3rd Gen Xeon Scaleable and PCIe support.

Something they touch on is Sapphire Rapids' PCIe 5.0 support. I wonder whether all implementations of Sapphire Rapids will actually run PCIe 5.0, or if we might see some workstation/server boards using cheaper PCIe 4.0-only designs.