News Intel Powers On Sapphire Rapids Processors, Scheduled for 2021

[JayNor]

I wonder whether all implementations of Sapphire Rapids will actually run PCIe 5.0, or if we might see some workstation/server boards using cheaper PCIe 4.0-only designs.

PCIE5 will handle prior versions of PCIE so, for example, it will be compatible with their recently announced PCIE4 Optane SSDs and with the current Habana NNPs.

The CXL asymmetric cache coherency depends on some feature of PCIE5. They've already announced plans for CXL support in a coming agilex FPGA version and in the Ponte Vecchio GPU. Unknown now what are the pcie versions of the other coming discrete Xe GPUs.

 

[JayNor]

Without PCIe 4.0 the new nVidia systems won't work.

Probably not true due to backward compatibility requirements in the PCIE4 spec.

Anyway, Intel has been sampling Ice Lake Server chips with PCIE4 since June 2019, and they also have Stratix 10 DX FPGAs from around the same time with fully qualified PCIE4 operation.

I don't recall seeing any exclusive agreement announced between AMD and NVDA on use of NVDA's new GPUs, so won't be surprised to see Ice Lake Server boards that incorporate the new NVDA GPUs.

 

[JayNor]

Single Socket Epyc - 128 PCIe4 Lanes, as well.

Anyway, I don't get how this is winning - Intel has to go dual-socket for 128 lanes, yet that gives them only 76 cores (allegedly) vs. AMD's 128.

It would be winning if someone wants to use Optane DIMMS or AVX512 operations along with their PCIE4 accesses.

 

[JayNor]

AVX-512 has basically been a mess, and AMX seems like yet another example of Intel not knowing when to leave well-enough alone. Of course, it's for AMD if Intel continues to make their cores ever-larger and more complex.

AVX2 and AVX512 are very much the same mess. Rumors are that AMD will add AVX512 in zen4.

The new AMX tiled fma matrix operations look like a natural update to incorporate features that are popping up in the NNP ASICs. Intel is just starting with these.

AMD may prefer to steer customers to GPU solutions. Seems to be their current position in response to AVX512 questions. I'm curious why the change of strategy in zen4, if it indeed will get AVX512 operations.

The "ever-larger" complaint ... Intel is moving to 10nm at the same time as adding AMX, so the processors might actually be smaller.

Some of the AVX512 performance problems are thermal issues, which should also be relieved somewhat by the move to 10nm.

 

[bit_user]

PCIE5 will handle prior versions of PCIE so,

That's beside the point.

PCIe 5.0 adds significant cost and complexity to a board. Therefore, if a given market segment doesn't require it, I suspect we'll see boards that only support up to PCIe 4.0, with this chipset.

The CXL asymmetric cache coherency depends on some feature of PCIE5. They've already announced plans for CXL support in a coming agilex FPGA version and in the Ponte Vecchio GPU.

Only a small number of Sapphire Rapids-based systems will have those. The majority of server workloads don't use GPUs or FPGAs.

 

[bit_user]

AVX2 and AVX512 are very much the same mess.

Not at all.

• AVX-512 has over a half-dozen subsets, and not a single Intel CPU implements all of it.
• AVX-512 adds a lot of die area and significant clock-throttling, if you use it (in some cases, much worse than AVX2 ever did).
• AVX-512 has a performance pitfall, where if you execute a single AVX-512 instruction without resetting the vector state, afterwards, all of your subsequent 128-bit and 256-bit operations have an added penalty, because the CPU now has to treat the upper 256-bits of every vector as valid, meaning a lot of extra data has to get shuffled around.

Rumors are that AMD will add AVX512 in zen4.
...
I'm curious why the change of strategy in zen4, if it indeed will get AVX512 operations.

I've heard that. It would be unfortunate, but I can imagine a lot of customers are asking for it, since they assume it's basically "free" and would like there to be no potential downside to switching between AMD and Intel CPUs.

The new AMX tiled fma matrix operations look like a natural update to incorporate features that are popping up in the NNP ASICs.

It's flawed thinking to try and stuff every feature into a CPU! This is the whole reason we have GPUs and Deep Learning ASICS!

Intel is just starting with these.

Intel just can't stop seeing x86 as the solution to every problem!

It reminds me of the mainframe era, where ever more complexity just kept getting added to the instruction set and they ultimately couldn't compete with cheaper, simpler RISC CPUS. Intel is making these phenomenally huge and complex cores that are going to be vastly more expensive than ARM or even Zen2 cores, and then left wondering why they keep losing customers.

The "ever-larger" complaint ... Intel is moving to 10nm at the same time as adding AMX, so the processors might actually be smaller.

The issue of concern isn't physical size, so much as cost. Their competition is on a comparable manufacturing node, so if the competitors' cores are shrinking more, then they can offer better performance per $. Even workloads that can benefit from AMX will still probably be more economical to run on a GPU.