News Intel Raptor Lake CPU Runs On 27-Year-Old Windows NT 4.0

Status
Not open for further replies.
@zhiyeliu
It's remarkable to see how a 27-year-old Windows operating system supports a modern processor, such as Raptor Lake, not to mention a chip with a hybrid design.
The i3-13100F is not hybrid! However, it does have hyperthreading (but no iGPU, as noted). However, I'm skeptical NT 4.0 would've supported HT on the Pentium 4, since I think it only arrived on the later Northwood steppings, which launched rather late into the Windows 2000 era. I'm guessing he probably disabled HT in the BIOS.

Also, although it's marketed as Raptor Lake, the actual die seems to be identical to the smaller Alder Lake-S (i.e. probably the same).

BTW, I wonder what's the highest resolution the X300 supports - or, rather the best graphics card you can get to work in it. It'd be great to do some retro gaming at 1440p/60 Hz with max settings.
 
@zhiyeliu

The i3-13100F is not hybrid! However, it does have hyperthreading (but no iGPU, as noted). However, I'm skeptical NT 4.0 would've supported HT on the Pentium 4, since I think it only arrived on the later Northwood steppings, which launched rather late into the Windows 2000 era. I'm guessing he probably disabled HT in the BIOS.

Also, although it's marketed as Raptor Lake, the actual die seems to be identical to the smaller Alder Lake-S (i.e. probably the same).

BTW, I wonder what's the highest resolution the X300 supports - or, rather the best graphics card you can get to work in it. It'd be great to do some retro gaming at 1440p/60 Hz with max settings.
The first P4 that supported HT was the 3.06 GHz model released on November 14, 2002.
 
The first P4 that supported HT was the 3.06 GHz model released on November 14, 2002.
Yup, and that was a later iteration of Northwood, but still had a 533 MHz FSB. They would eventually release a model with 800 MHz FSB, but the main focus of both those features (plus double the L2 cache) was Prescott.

I wanted Prescott's new instructions (SSE3) & larger cache and was skeptical it was as bad as everyone said, so I went ahead and bought one (upgrading from a Pentium Pro). The main issue I had is just that my heatsink would get clogged with dust and then the CPU would overheat/throttle. Back then, the throttling wasn't subtle. So, I ended up having to dust my PC about twice per year, until I replaced it. I also made sure my next case had dust filters and a larger CPU heatsink with a slower fan.
 
Yup, and that was a later iteration of Northwood, but still had a 533 MHz FSB. They would eventually release a model with 800 MHz FSB, but the main focus of both those features (plus double the L2 cache) was Prescott.

I wanted Prescott's new instructions (SSE3) & larger cache and was skeptical it was as bad as everyone said, so I went ahead and bought one (upgrading from a Pentium Pro). The main issue I had is just that my heatsink would get clogged with dust and then the CPU would overheat/throttle. Back then, the throttling wasn't subtle. So, I ended up having to dust my PC about twice per year, until I replaced it. I also made sure my next case had dust filters and a larger CPU heatsink with a slower fan.
Northwood. Will always remember my Northwood 1.6A that did 2.7Ghz. Would lock after a couple hours of Prime95. So everyday I think was 2.54Ghz which ran 24/7. Loved that setup..
 
  • Like
Reactions: bit_user
Still have the screenshot. Haha. (Think my hard drives were two WD 120's in RAID)

Northwood 1.6A

Sorry didnt mean to go off topic. Liked NT 4.0, but it was a pain with IRQ's when you added too much hardware. Micron Computers from factory could come with the Intel Seattle 2 motherboard, 2 IRQ's I think for the Crystal Audio onboard sound. Adaptec 2940 SCSI Card, NIC, 3Dfx Monster II, Viper V550, and sometimes a USR 56k Win modem. All drivers installed via Driver disks. I did phone support for those back in the day, and you dreaded a reload with that hardware and NT 4.0. But those were great times back then.
 
  • Like
Reactions: bit_user
That depends on your definition of "software."
The only time a CPU runs on an OS is when the CPU is simulated. This is not one of those times. The CPU or hardware as a whole sits at the very bottom of the tech stack. It doesn't matter what your definition of software is, microcode, bootloader, kernel, BIOS, OS, Programs are all software because they can be changed by someone after manufacturing. Software always will be on physical hardware. Never the other way around.
 
  • Like
Reactions: bit_user
That title is backwards. Software runs on CPUs, CPUs don't run on software.

It should say "27-Year-Old Windows NT 4.0 Runs On Intel Raptor Lake CPU". Was this written by AI?
AI or major brain fart day

"We see feats of users getting retro hardware to work on old versions of Windows and vice versa."

You don't get old hardware to work on old versions. And getting old versions to work on old hardware is not remotely close to any feat.

And vice versa?
Get modern hardware to work on new versions?
 
  • Like
Reactions: bit_user
Then what is the definition of "software" that would satisfy "CPU runs on software"?
The only time a CPU runs on an OS is when the CPU is simulated. This is not one of those times. The CPU or hardware as a whole sits at the very bottom of the tech stack. It doesn't matter what your definition of software is, microcode, bootloader, kernel, BIOS, OS, Programs are all software because they can be changed by someone after manufacturing. Software always will be on physical hardware. Never the other way around.
CPUs are run on several layers like an onion. The lowest layer is the microcode which translates higher level instructions into something a CPU can use to work. Microcode is software as defined by google; "the programs and other operating information used by a computer." Since microcode is firmware that allows CPUs to do its work, one could say that a CPU runs on microcode. Without microcode a CPU is a paperweight.
 
  • Like
Reactions: bit_user
CPUs are run on several layers like an onion. The lowest layer is the microcode which translates higher level instructions into something a CPU can use to work. Microcode is software as defined by google; "the programs and other operating information used by a computer." Since microcode is firmware that allows CPUs to do its work, one could say that a CPU runs on microcode. Without microcode a CPU is a paperweight.
Microcode in this case is only really pertinent for more complicated instructions. If Intel hasn't changed their design much in terms of "big picture" elements since the Core microarchitecture, then the instruction decoder is split up into two main categories: simple and complex.

Simple instructions are decoded into micro-ops directly by hardware. For example, the MOV instruction in x86 is straight forward. A basic ADD instruction is also fairly straight forward, the only complication is needing to know if the arguments are a memory location or not (since if it were being translated into something RISC like, would need a MOV equivalent, then an ADD). Also if you think about it, this is important from a performance standpoint: if you have to go through a software program for every instruction, it's going to be much slower than to simply have hardware do it. And you'd have to have a really bad day to screw up the hardware circuitry for a simple ADD instruction.

See https://www.realworldtech.com/nehalem/5/, if you look at the diagram, the only thing touching the Microcode, or μCode as labeled in the diagram, is the complex decoder.

Besides that, if you know the specific way the circuitry is expecting instructions, you wouldn't need microcode. But the problem is if you program this way, it'll only work for that exact circuitry.
 
Last edited:
  • Like
Reactions: helper800
Microcode in this case is only really pertinent for more complicated instructions. If Intel hasn't changed their design much in terms of "big picture" elements since the Core microarchitecture, then the instruction decoder is split up into two main categories: simple and complex.

Simple instructions are decoded into micro-ops directly by hardware. For example, the MOV instruction in x86 is straight forward. A basic ADD instruction is also fairly straight forward, the only complication is needing to know if the arguments are a memory location or not (since if it were being translated into something RISC like, would need a MOV equivalent, then an ADD). Also if you think about it, this is important from a performance standpoint: if you have to go through a software program for every instruction, it's going to be much slower than to simply have hardware do it. And you'd have to have a really bad day to screw up the hardware circuitry for a simple ADD instruction.

See https://www.realworldtech.com/nehalem/5/, if you look at the diagram, the only thing touching the Microcode, or μCode as labeled in the diagram, is the complex decoder.

Besides that, if you know the specific way the circuitry is expecting instructions, you wouldn't need microcode. But the problem is if you program this way, it'll only work for that exact circuitry.
I am not as familiar with the specifics as you are in regards to microcode, but this is basically what I meant by saying "higher level instructions." A CPU's microcode is a layer between whatever instruction set architecture the PC is sending its way and the CPU itself. Since most instructions sent to the CPU are complex or are parts of a larger whole, microcode is utilized in almost every task. Microcode is itself a set of hardware level instructions that implement machine code. Machine code is basically a very specific kind of instruction like a load, store, jump, or an ALU operation. I am certainly no expert, clearly, but I do know most of the basics. Please correct me if I am making some sort of mistake.
 
I am not as familiar with the specifics as you are in regards to microcode, but this is basically what I meant by saying "higher level instructions." A CPU's microcode is a layer between whatever instruction set architecture the PC is sending its way and the CPU itself. Since most instructions sent to the CPU are complex or are parts of a larger whole, microcode is utilized in almost every task. Microcode is itself a set of hardware level instructions that implement machine code. Machine code is basically a very specific kind of instruction like a load, store, jump, or an ALU operation. I am certainly no expert, clearly, but I do know most of the basics. Please correct me if I am making some sort of mistake.
Yes, you're correct in saying that microcode translates the ISA based instructions into something the control unit and execution unit actually acts upon. However, it's incorrect to say that everything runs on microcode, because the instruction decoder can handle so-called simple instructions directly.

Microcode is only a concern with certain complex operations because they can be hard to get right the first time and extensive testing is not feasible. But you don't need this for basic CPU instructions like MOV or ADD.

In fact, most native RISC implementations don't have microcode. Example, ARM's Cortex A710:
a710_revised.drawio.jpg


Note that "micro-op" is not the same as microcode.

If you're confused as to the difference between microcode and microoperation (from this)
Microcode is a micro-program made up of micro-instructions which are directly executed by the hardware. It is an interpreter for the machine code the programmer sees, in much the same way as traditional BASIC is for a tokenised BASIC program. Micro-instructions generally look nothing like the user-visible machine language.

A micro-op is also an instruction that is directly executed by the hardware. In a RISC CPU machine code instructions and micro-ops mostly have a 1:1 relationship.
 
Last edited:
  • Like
Reactions: helper800
CPUs are run on several layers like an onion. The lowest layer is the microcode which translates higher level instructions into something a CPU can use to work. Microcode is software as defined by google; "the programs and other operating information used by a computer." Since microcode is firmware that allows CPUs to do its work, one could say that a CPU runs on microcode.
"Since microcode is firmware that allows CPUs to do its work"

No microcode standardizes the way for software to communicate with the CPU.

"one could say that a CPU runs on microcode."

Microcode allows any software above it in the stack to have a standardized process.

"Without microcode a CPU is a paperweight."

Without microcode if I manually send electrical signals to the logic gates inside the CPU it will give me the correct output. Without every layer of the tech stack it gets infinitely more difficult to have it to generate the outcome you want it to but not entirely impossible.

This type of logic comes from the same flawed English of 'this car runs on petrol'.People say it wrongly enough times others stop caring about its grammatical innaccuracy. The car uses petrol as a fuel with a spark to create micro explosions that pushes the pistons in a predetermined optimized sequence to rotate a crankshaft that then through a complex system of flywheel, clutch, transmission(maybe some other things I don't know about). Make it easier for the person to use the car. Imagine turning on the car and the car starts moving forward at max speed or have a absurd single gear that allows the 1600bhp car to move like a snail. Same reason there are multiple layers of abstraction on a computer to allow the user to adjust the speed vs easier usability of the computer.
 
Last edited:
  • Like
Reactions: helper800
Yes, you're correct in saying that microcode translates the ISA based instructions into something the control unit and execution unit actually acts upon. However, it's incorrect to say that everything runs on microcode, because the instruction decoder can handle so-called simple instructions directly.

Microcode is only a concern with certain complex operations because they can be hard to get right the first time and extensive testing is not feasible. But you don't need this for basic CPU instructions like MOV or ADD.

In fact, most native RISC implementations don't have microcode. Example, ARM's Cortex A710:
a710_revised.drawio.jpg


Note that "micro-op" is not the same as microcode.

If you're confused as to the difference between microcode and microoperation (from this)
"Since microcode is firmware that allows CPUs to do its work"

No microcode standardizes the way for software to communicate with the CPU.

"one could say that a CPU runs on microcode."

Microcode allows any software above it in the stack to have a standardized process.

"Without microcode a CPU is a paperweight."

Without microcode if I manually send electrical signals to the logic gates inside the CPU it will give me the correct output. Without every layer of the tech stack it gets infinitely more difficult to have it to generate the outcome you want it to but not entirely impossible.

This type of logic comes from the same flawed English of 'this car runs on petrol'.People say it wrongly enough times others stop caring about its grammatical innaccuracy. The car uses petrol as a fuel with a spark to create micro explosions that pushes the pistons in a predetermined optimized sequence to rotate a crankshaft that then through a complex system of flywheel, clutch, transmission(maybe some other things I don't know about). Make it easier for the person to use the car. Imagine turning on the car and the car starts moving forward at max speed or have a absurd single gear that allows the 1600bhp car to move like a snail. Same reason there are multiple layers of abstraction on a computer to allow the user to adjust the speed vs easier usability of the computer.
The more I think I know the more I end up learning I know nothing. I love this website... Thanks for the information gents.
 
  • Like
Reactions: omnitrixpower95
the instruction decoder is split up into two main categories: simple and complex.

Simple instructions are decoded into micro-ops directly by hardware. For example, the MOV instruction in x86 is straight forward. A basic ADD instruction is also fairly straight forward, the only complication is needing to know if the arguments are a memory location or not (since if it were being translated into something RISC like, would need a MOV equivalent, then an ADD). Also if you think about it, this is important from a performance standpoint: if you have to go through a software program for every instruction, it's going to be much slower than to simply have hardware do it. And you'd have to have a really bad day to screw up the hardware circuitry for a simple ADD instruction.

See https://www.realworldtech.com/nehalem/5/, if you look at the diagram, the only thing touching the Microcode, or μCode as labeled in the diagram, is the complex decoder.
According to this paper:

"Most Intel CPUs have multiple decoders: several simple decoders to translate x86 instructions that map to a single μop, a complex decoder to translate instructions that map to 1-4 μops, and a Microcode Sequencer responsible for translating microcoded instructions. Microcoded instructions are the most complex instructions that require advanced logic to be executed. Examples are cpuid that returns detailed information about the CPU and wrmsr that modifies internal settings in model-specific registers (MSRs)."

it's incorrect to say that everything runs on microcode, because the instruction decoder can handle so-called simple instructions directly.
That's not true. Every x86 instruction gets translated into a micro-op. Even if it's a 1:1 translation, there's still a translation.

Again, from the above paper (Introduction, first paragraph):

"Microcode is the hidden software layer between the instruction set and the underlying hardware. In most Complex Instruction Set Architectures (CISC), each instruction, or macro-instruction, is translated into one or more micro-operations (μops) that are executed by the underlying hardware. In total, there are over 2700 distinct μops in Intel x86. Many simple instructions map to a single μop. However, more complex instructions are essentially entire programs and can map to > 50 μops. Microcode is a crucial optimization for these instructions, as μops are much simpler to implement in hardware and can be pipelined more efficiently."

If you want to understand how microcode truly works in modern CPUs, definitely read that paper. I only read the Abstract, Intro, and Background sections. That's only 2.5 pages and will increase your understanding, greatly.

Microcode is only a concern with certain complex operations because they can be hard to get right the first time and extensive testing is not feasible. But you don't need this for basic CPU instructions like MOV or ADD.
I wouldn't be too sure about that. If we're talking x86, even mov isn't as simple as you probably think it is. If you mean register-to-register copy, then sure. Likewise, add can have memory operands and those can involve address arithmetic.

In fact, most native RISC implementations don't have microcode. Example, ARM's Cortex A710:
a710_revised.drawio.jpg


Note that "micro-op" is not the same as microcode.
Don't read too much into that diagram. It's a reconstruction (i.e. not-authoritative) meant only for illustrative purposes. Also, if modern CPUs don't implement microcode in micro-ops, then what?

If you're confused as to the difference between microcode and microoperation
IMO, it's a slightly artificial distinction. The instruction decoders are an indirection layer. What the CPU executes are micro ops. The microcode could be seen as the definition of that translation layer.

I guess the distinction you could make is between microcoded and simpler instructions. However, depending on how many instructions could be potentially microcoded, you could still say it's the microcode, writ large, which defines how programs are run on the CPU.
 
Last edited:
  • Like
Reactions: helper800
Without microcode if I manually send electrical signals to the logic gates inside the CPU it will give me the correct output. Without every layer of the tech stack it gets infinitely more difficult to have it to generate the outcome you want it to but not entirely impossible.
You were correct to say it serves the purpose of standardizing the working of the CPU. I choose these words carefully, because it's not only the instruction format which matters, but also their behavior.

Something like a GPU doesn't need microcode, because it doesn't need to publish or maintain a standard ISA. If the hardware has a bug, this bug can be fixed by altering the instruction sequence generated by the shader compiler. If a subsequent version of the hardware needs to change the instruction syntax or semantics, it can do so without breaking compatibility, because games are meant to use a standard shader language and not contain GPU assembly language.

Not having the indirection existing at the hardware level doesn't make it infinitely more difficult - all we've done is move that translation step from hardware to software.
 
  • Like
Reactions: helper800
That's not true. Every x86 instruction gets translated into a micro-op. Even if it's a 1:1 translation, there's still a translation.
You misunderstand me, but it could just be poorly worded. If the instruction can be decoded in the simple decoder, it doesn't need to go through the microcode routine, hence , handles it directly.

I wouldn't be too sure about that. If we're talking x86, even mov isn't as simple as you probably think it is. If you mean register-to-register copy, then sure. Likewise, add can have memory operands and those can involve address arithmetic.
I'm aware of different types of operands in x86 instructions. However, whatever constitutes a "simple instruction" is up in the air because if we go back to https://www.realworldtech.com/nehalem/5/, it says SSE instructions go through the simple decoder.

Don't read too much into that diagram. It's a reconstruction (i.e. not-authoritative) meant only for illustrative purposes. Also, if modern CPUs don't implement microcode in micro-ops, then what?
Then find me one that is authoritative.

IMO, it's a slightly artificial distinction. The instruction decoders are an indirection layer. What the CPU executes are micro ops. The microcode could be seen as the definition of that translation layer.
If we want to get super anally technical, then sure, we could split up the instruction decoder into two areas: the hardwired microcode and the microcode that can be updated because it handles complicated instructions that may need to be updated in case of an issue.

But then we may as well say every damn CPU in existence runs on microcode because every instruction decoder is hardwired microcode.
 
  • Like
Reactions: helper800
If the instruction can be decoded in the simple decoder, it doesn't need to go through the microcode routine, hence , handles it directly.
Ah, but who's to say that mapping is fixed? Maybe a microcode update switches a given x86 instruction from being simple to complex, or even fully-microcoded? Simple decoders aren't necessarily fixed, in terms of the opcodes they handle.

I'm aware of different types of operands in x86 instructions. However, whatever constitutes a "simple instruction" is up in the air because if we go back to https://www.realworldtech.com/nehalem/5/, it says SSE instructions go through the simple decoder.
What's interesting is that AVX2 gather instructions had that recent microcode mitigation. That means either they're not simple, or that simple decoders are runtime-configurable.


Then find me one that is authoritative.
That would be ARM's proprietary information.

we could split up the instruction decoder into two areas: the hardwired microcode and the microcode that can be updated because it handles complicated instructions that may need to be updated in case of an issue.
I think you don't mean "hardwired microcode", but rather hardwired x86 -> micro-op translation. I'm just not sure even the simple decoders are actually hardwired, or at least without an override mechanism.

But then we may as well say every damn CPU in existence runs on microcode because every instruction decoder is hardwired microcode.
I think not all CPUs have this distinction between external and internal instructions/ops. It's more likely the tiny, in-order cores found in things like microcontrollers and DSPs that lack a translation layer. Such embedded processors can afford to make developers recompile for each generation of the hardware.

Also, anything which supports exclusively JIT-compilation, such as GPUs traditionally do. Funny thing about GPUs is that even if they publish an assembly language spec, as AMD now does, the device driver can modify that code as it's being loaded onto the GPU. So, you can also implement bug fixes at that level.
 
Last edited:
  • Like
Reactions: helper800
Status
Not open for further replies.