News Intel Razer Lake, Nova Lake, and Wildcat Lake CPU PCI IDs added to Linux

[Admin]

Linux Kernel patches list seven new PCI IDs associated with upcoming CPUs from Intel.

Intel Razer Lake, Nova Lake, and Wildcat Lake CPU PCI IDs added to Linux : Read more

 

[usertests]

Put Wildcat Lake in our hands ASAP

 

[bit_user]

Put Wildcat Lake in our hands ASAP

Sadly, their E-core SoCs have be lagging everything else, the past few generations. They're low-margin parts, so they get lower priority and might not even be viable until the process is mature.

I'm still happy with my Alder-N mini-server, for now. However, they're definitely underpowered for a laptop and Twin Lake doesn't really do anything to change that.

 

[usertests]

Sadly, their E-core SoCs have be lagging everything else, the past few generations. They're low-margin parts, so they get lower priority and might not even be viable until the process is mature.

I'm still happy with my Alder-N mini-server, for now. However, they're definitely underpowered for a laptop and Twin Lake doesn't really do anything to change that.

It's almost too good to be true for the described Wildcat Lake to become a low margin product and true successor to the Atom line. Depends on 18A and the die size.

Even if they typically disabled the chip down to 1+3, both the Cougar Cove and Darkmont cores would be delivering a huge single-thread uplift. That would be the payoff from moving to a heterogeneous design at the low-end. And it's what low-end systems need, not 8-16 little cores.

Twin Lake might have some unexpectedly good out-of-the-box graphics performance, but that's about it.

 

[bit_user]

It's almost too good to be true for the described Wildcat Lake to become a low margin product and true successor to the Atom line. Depends on 18A and the die size.

Even if they typically disabled the chip down to 1+3, both the Cougar Cove and Darkmont cores would be delivering a huge single-thread uplift. That would be the payoff from moving to a heterogeneous design at the low-end. And it's what low-end systems need, not 8-16 little cores.

All of this makes me suspicious it's truly a Alder-N successor. I think maybe they're subdividing that market, but still expect them to make E-only SoCs for the bottom tier.

Twin Lake might have some unexpectedly good out-of-the-box graphics performance, but that's about it.

I wish (but don't think we've seen?) they'd double the L2 cache, like they did in Raptor Lake. I also wonder whether it's using Raptor Lake's process node, but then I'd expect more than the modest 100 MHz clock speed bump that's been reported.

 

[usertests]

I wish (but don't think we've seen?) they'd double the L2 cache, like they did in Raptor Lake. I also wonder whether it's using Raptor Lake's process node, but then I'd expect more than the modest 100 MHz clock speed bump that's been reported.

It's definitely the same silicon. But the N150 gets +250 MHz and N250 gets +500 MHz to the iGPU turbo clock, which is nice. That puts the N250 iGPU a little above N95/N97 and matching N300/N305.

Obviously, clock speed isn't everything for graphics, but +67% iGPU turbo is a lot more significant than +2.7% CPU turbo (for N250 vs. N200).

https://videocardz.com/newz/intel-nx50-twin-lake-e-core-cpu-specs-have-been-leaked

 

[subspruce]

It's almost too good to be true for the described Wildcat Lake to become a low margin product and true successor to the Atom line. Depends on 18A and the die size.

Even if they typically disabled the chip down to 1+3, both the Cougar Cove and Darkmont cores would be delivering a huge single-thread uplift. That would be the payoff from moving to a heterogeneous design at the low-end. And it's what low-end systems need, not 8-16 little cores.

Twin Lake might have some unexpectedly good out-of-the-box graphics performance, but that's about it.

except E cores can only be in sets of 4 so it would be 1+4, so here's my nitpick

 

[subspruce]

All of this makes me suspicious it's truly a Alder-N successor. I think maybe they're subdividing that market, but still expect them to make E-only SoCs for the bottom tier.

if Wildcat lake is an Alder-N successor:
- 8 Skymont E cores
- Xe2 graphics (still 2 Xe cores)
- Intel 3 process

 

[bit_user]

except E cores can only be in sets of 4 so it would be 1+4, so here's my nitpick

The N50 has all but 2 E-cores disabled. Intel can clearly disable as many as it wants, but I guess they've mostly stuck to having entire clusters enabled or disabled.

I think an interesting possibility would've been for them to enable two E-cores in each cluster, so they'd each get double the effective L2 cache. For whatever reason, it seems Intel hasn't gone down this road.

 

[bit_user]

if Wildcat lake is an Alder-N successor:
- 8 Skymont E cores
- Xe2 graphics (still 2 Xe cores)
- Intel 3 process

That's not what's been leaked about it, though. Supposedly it pairs Cougar Cove P-cores and Darkmont LPE-cores in a 2P+4LPE configuration:

https://www.tomshardware.com/pc-com...cougar-cove-and-darkmont-cores-intel-18a-node
​

If you're speaking hypothetically, then I'd agree. For me, the big question would be how well Skymont backports to Intel 3, because it might end up being too big and/or clocking too low. In that case, they'd have to stick with Crestmont (which isn't a lot better than Gracemont).

 

[usertests]

except E cores can only be in sets of 4 so it would be 1+4, so here's my nitpick

As @bit_user said, the lowly N50 proves they can disable the E-cores in pairs at least. If they can't also disable 1 E-core in the cluster, then I don't know what they've bothered designing.

My own nitpick: they are actually LP E-cores according to the leak. Wildcat Lake sounds a lot like a discount version of Lunar Lake, maybe monolithic, but with newer cores.

 

[subspruce]

The N50 has all but 2 E-cores disabled. Intel can clearly disable as many as it wants, but I guess they've mostly stuck to having entire clusters enabled or disabled.

I think an interesting possibility would've been for them to enable two E-cores in each cluster, so they'd each get double the effective L2 cache. For whatever reason, it seems Intel hasn't gone down this road.

It's simpler to fuse off an entire cluster. Intel has never made an E core in a cluster of 3. It's always been 4 or 2. Either the segmentation doesn't need clusters of 3 of E cores or it's impossible.