Intel didn't change the L3 cache per core configuration from ADL to RPL so that's not a thing.
Since you don't seem to grasp this I'll try a more in depth explanation.
First Intel doesn't call it by it's architecture name on Ark just slots them into the "family".
Now the more important part is the die themselves:
ADL using the GC core has two die that are being manufactured C0 which is 8P/8E and H0 which is 6P/0E. Every ADL CPU with E cores uses the C0 die from the 6P/4E to the 8P/8E. I'd have to go through and double check, but I believe every ADL CPU without E cores uses the H0 die.
RPL using the RC core only has a single die being manufactured which is B0 that has 8P/16E. This is where things differ from ADL only the 65W parts on the list in this article use B0 die. I'll use the 13600 and 13600K as the easiest example of this:
Note the 11.5MB of L2 on the 13600 and then if you go to ordering and compliance it says C0 for die:
https://ark.intel.com/content/www/u...13600-processor-24m-cache-up-to-5-00-ghz.html
Note the 20MB of L2 on the 13600K and then under ordering and compliance it says B0 for die:
https://ark.intel.com/content/www/u...3600k-processor-24m-cache-up-to-5-10-ghz.html
Now as for what I said about configuration if you look at the 13400 it shows 11.5MB L2 cache, but when you go to ordering and compliance it says it uses both the B0 and C0 die. One of these is GC ADL and the other is RC RPL, but both are configured to have the specifications of ADL:
https://ark.intel.com/content/www/u...13400-processor-20m-cache-up-to-4-60-ghz.html