Intel Reportedly Puts Up 5GHz Core i9-9990XE CPU For Auction

[Olle P]

Dropping legacy support would simplify the instruction decoders...

I suppose that would make it RISC-like compared to the current x86, which would speed things up.

 

[InvalidError]

Dropping legacy support would simplify the instruction decoders...

I suppose that would make it RISC-like compared to the current x86, which would speed things up.

Not really, x86's back-end (the part that deals with uOps and gets all of the heavy lifting done) is already practically pure RISC and wouldn't get any faster from eliminating instruction decoders. It may even get slower since many CISC instructions would get replaced by 2-5 larger RISC instructions, consuming more cache and memory bandwidth. All you save by going full RISC is a tiny bit of die area, a little power and one or two cycles reduced latency on branch prediction misses. Under normal circumstances, the execution pipeline is running off the trace/uOp cache instead of decoders.