News Intel Reveals Three new Cutting-Edge Packaging Technologies

vaughn2k

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Aug 6, 2008
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This is not cutting edge. This assembly (not packaging please!!) technology has been existing for 10 years, and already being used by Philips, NXP, as well as STMicro and Toshiba. Its just Intel made it larger, and better reliable because of the size, and regardless of its assembly technology name.
This is not new anymore.
 

InvalidError

Titan
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1000+ micro-bumps per square millimeter? Yikes, those are going to be some awfully small solder joints. Some serious material science must be going in there to prevent those from breaking under thermal expansion/contraction cycles.
 
Another bunch of slide and another bunch of prototypes that nobody has a clue if they work. Another attempt at manipulating the message and saying "Hey, we are here and we have more chiplets!!!"

While at the same time... Sunnycove exist... just saying...
 
Another bunch of slide and another bunch of prototypes that nobody has a clue if they work. Another attempt at manipulating the message and saying "Hey, we are here and we have more chiplets!!!"

While at the same time... Sunnycove exist... just saying...

Don't think its all a prototype. They are already shipping some products using this and this will probably be in their next server CPU. Its similar, although more advanced, to AMDs chiplet design. If AMD can do it wouldn't you think a company that can spend more than AMD earns in a few years on FABs could figure it out too?

Another "new" technology from Intel >gasp< and on the heels of the Zen 2 release!

My heart is all a-flutter!

Well, not really, but it looks like Intel is feeling ignored, so I'll play along.

You are right. Intel should just stop trying new ideas and never report about them at all ever.

Or they should continue to try new ideas and give nice new ground breaking ones that benefit everyone eventually much like Thunderbolt which will be integrated into USB 4.
 
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LOL....I got tired of advance announcements during the era of non-stop vaporware.

When it hits the streets, and is well documented, only then will I bother to care.

Agilex will ship in Q3 2019:

https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.html

Uses both EMiB and 3D stacking technologies.

And announcements or this are never a bad thing. A lot of times they end up in other products. For example Intels Terascale ended up in the Xeon Phi products that powered HPCs.
 
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More like since 2007 if you count their Terascale processor design which had a CPU stacked on top of memory:


They even hit 1TB/s worth of bandwidth back then too.

So are you talking R&D or special/outlying applications? What actual production devices were these in?

* Waits for you to grasp the point *

There you have it. So yes, AMD beat them to production of widespread consumer devices using the technology. Intel is only just catching up.
 
So are you talking R&D or special/outlying applications? What actual production devices were these in?

* Waits for you to grasp the point *

There you have it. So yes, AMD beat them to production of widespread consumer devices using the technology. Intel is only just catching up.

I never said they beat them to the consumers. Just that Intel had made products that used the technology before AMD ever did.